Abhijit Dharchoudhury - researchr alias

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1999

Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit SizingSupamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw. dac 1999: 436-441 [doi]

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing AnalysisSavithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury. vlsid 1999: 175-180 [doi]

1998

1997

Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC MicroprocessorAbhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning. iccd 1997: 143-148

Library-less synthesis for static CMOS combinational logic circuitsSergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw. iccad 1997: 658-662 [doi]

1996

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI ChipsYi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang. dac 1996: 548-551 [doi]

1995

Worst-case analysis and optimization of VLSI circuit performancesAbhijit Dharchoudhury, Sung-Mo Kang. tcad, 14(4):481-492, 1995. [doi]

1994

Fast timing simulation of transient faults in digital circuitsAbhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel. iccad 1994: 719-722 [doi]

Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristicsAbhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S.-H. Lee. iccad 1994: 190-194 [doi]

1993

Performance-Constrained Worst-Case Variability Minimization of VLSI CircuitsAbhijit Dharchoudhury, Sung-Mo Kang. dac 1993: 154-158 [doi]

1992

An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog CircuitsAbhijit Dharchoudhury, Sung-Mo Kang. dac 1992: 704-709 [doi]