Chihong Zhang - researchr alias

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Viewing Publication 1 - 9 from 9

2003

Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar ArchitecturesRamaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao. TC, 52(1):4-20, 2003. [doi]

2001

Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGsRamaswamy Govindarajan, Hongbo Yang, Chihong Zhang, José Nelson Amaral, Guang R. Gao. ipps 2001: 26

1999

Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue ProcessorsRamaswamy Govindarajan, Chihong Zhang, Guang R. Gao. lcpc 2000: 70-84 [doi]

Efficient State-Diagram Construction Methods for Software PipeliningChihong Zhang, Ramaswamy Govindarajan, Sean Ryan, Guang R. Gao. cc 1999: 153-167

1997

A New Architecture For Branch-Intensive LoopsZhizhong Tang, Chihong Zhang, Sifei Lvand, Tao Yu. apdc 1997: 241-247 [doi]

Control Mechanism for Software Pipelining on Nested LoopTao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo. apdc 1997: 345-350 [doi]

An Improvement on Data Dependence Analysis Supporting Software Pipelining TechniqueChihong Zhang, Zhizhong Tang. apdc 1997: 378-382 [doi]

1993

URPR-1: A single-chip VLIW architectureBogong Su, Jian Wang, Zhizhong Tang, Chihong Zhang, Wei Zhao. jsa, 39(1):25-41, 1993. [doi]

GPMB - software pipelining branch-intensive loopsZhizhong Tang, Gang Chen, Chihong Zhang, Yingwei Zhang, Bogong Su, Stanley Habib. euromicro 1993: 21-30 [doi]

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