Chris H. Kim - researchr alias

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2011

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown CharacterizationJohn Keane, S. Venkatraman, Paulo F. Butzen, Chris H. Kim. tvlsi, 19(5):787-795, 2011. [doi]

Guest editors introduction: Nanoscale Memories Pose Unique ChallengesChris H. Kim, Leland Chang. dt, 28(1):6-8, 2011. [doi]

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS CircuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. tvlsi, 19(4):603-614, 2011. [doi]

2010

2009

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53 less static power than a power-gated SRAMKi Chul Chun, Pulkit Jain, Chris H. Kim. islped 2009: 119-120 [doi]

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering ResonanceJie Gu, Hanyong Eom, John Keane, Chris H. Kim. tvlsi, 17(9):1203-1211, 2009. [doi]

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICsJie Gu, Ramesh Harjani, Chris H. Kim. tvlsi, 17(2):292-301, 2009. [doi]

Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply IntegrityJie Gu, John Keane, Chris H. Kim. tvlsi, 17(1):128-136, 2009. [doi]

Adaptive techniques for overcoming performance degradation due to aging in digital circuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. aspdac 2009: 284-289 [doi]

2008

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization PropertyJie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim. tvlsi, 16(2):206-209, 2008. [doi]

A multi-story power delivery technique for 3D integrated circuitsPulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim. islped 2008: 57-62 [doi]

Enhancing ::::beneficial jitter:::: using phase-shifted clock distributionDong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim. islped 2008: 21-26 [doi]

Stack Sizing for Optimal Current Drivability in Subthreshold CircuitsJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. tvlsi, 16(5):598-602, 2008. [doi]

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive BoostingJonggab Kil, Jie Gu, Chris H. Kim. tvlsi, 16(4):456-465, 2008. [doi]

Circuit techniques for ultra-low power subthreshold SRAMsTae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim. iscas 2008: 2574-2577 [doi]

Body Bias Voltage Computations for Process and Temperature CompensationSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. tvlsi, 16(3):249-262, 2008. [doi]

2007

Modeling and estimating leakage current in series-parallel CMOS networksPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. glvlsi 2007: 269-274 [doi]

Subthreshold Leakage Modeling and Estimation of General CMOS Complex GatesPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. patmos 2007: 474-484 [doi]

Modeling Subthreshold Leakage Current in General Transistor NetworksPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. isvlsi 2007: 512-513 [doi]

Sleep transistor sizing and control for resonant supply noise dampingJie Gu, Hanyong Eom, Chris H. Kim. islped 2007: 80-85 [doi]

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage ShiftJie Gu, Sachin S. Sapatnekar, Chris H. Kim. dac 2007: 87-92 [doi]

An on-chip NBTI sensor for measuring PMOS threshold voltage degradationJohn Keane, Tae-Hyoung Kim, Chris H. Kim. islped 2007: 189-194 [doi]

Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit DesignTae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim. tvlsi, 15(7):821-829, 2007. [doi]

NBTI-Aware Synthesis of Digital CircuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. dac 2007: 370-375 [doi]

2006

Leakage Power Analysis and Reduction for Nanoscale CircuitsAmit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim. micro, 26(2):68-80, 2006. [doi]

Modeling and analysis of leakage induced damping effect in low voltage LSIsJie Gu, John Keane, Chris H. Kim. islped 2006: 382-387 [doi]

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizingJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. dac 2006: 425-428 [doi]

A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boostingJonggab Kil, Jie Gu, Chris H. Kim. islped 2006: 67-72 [doi]

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuitsChris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar. tvlsi, 14(6):646-649, 2006. [doi]

Utilizing reverse short channel effect for optimal subthreshold circuit designTae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim. islped 2006: 127-130 [doi]

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systemsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. aspdac 2006: 559-564 [doi]

An analytical model for negative bias temperature instabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. iccad 2006: 493-496 [doi]

Impact of NBTI on SRAM Read Stability and Design for ReliabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. isqed 2006: 210-218 [doi]

2005

2004

Leakage in nano-scale technologies: mechanisms, impact and design considerationsAmit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy. dac 2004: 6-11 [doi]

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOSHari Ananthan, Chris H. Kim, Kaushik Roy. islped 2004: 8-13 [doi]

2003

A forward body-biased low-leakage SRAM cache: device and architecture considerationsChris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy. islped 2003: 6-9 [doi]

Gate leakage reduction for scaled devices using transistor stackingSaibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy. tvlsi, 11(4):716-730, 2003. [doi]

2002

Dynamic VTH Scaling Scheme for Active Leakage Power ReductionChris H. Kim, Kaushik Roy. date 2002: 163-167 [doi]

Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessorsChris H. Kim, Kaushik Roy. islped 2002: 251-254 [doi]