Deshanand P. Singh - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 27 from 27

2024

Primate: A Framework to Automatically Generate Soft Processors for Network ApplicationsRui Ma, Jia-Ching Hsu, Ali Mansoorshahi, Joseph Garvey, Michael Kinsner, Deshanand P. Singh, Derek Chiou. cal, 23(1):57-60, January - June 2024. [doi]

2016

OpenCLDeshanand P. Singh, Peter Yiannacouras. In Dirk Koch, Frank Hannig, Daniel Ziener, editors, FPGAs for Software Programmers. pages 97-114, Springer, 2016. [doi]

2015

High-Level Design Tools for Floating Point FPGAsDeshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski. fpga 2015: 9-12 [doi]

2013

Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applicationsDoris Chen, Deshanand P. Singh. taco, 9(4):43, 2013. [doi]

Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platformsDoris Chen, Deshanand P. Singh. aspdac 2013: 297-304 [doi]

Harnessing the power of FPGAs using altera's OpenCL compilerDeshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling. fpga 2013: 5-6 [doi]

2012

Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filteringDoris Chen, Deshanand P. Singh. fpl 2012: 5-12 [doi]

From opencl to high-performance hardware on FPGASTomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh. fpl 2012: 531-534 [doi]

2007

2006

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAsGordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown. iccad 2006: 135-142 [doi]

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flowValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. slip 2006: 3-8 [doi]

2005

2004

The Quartus University Interface Program: enabling advanced FPGA researchShawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown. fpt 2004: 225-230 [doi]

2003

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic DevicesDeshanand P. Singh, Terry P. Borer, Stephen Dean Brown. vlsi 2003: 28-33

An Area-Efficient Timing Closure Technique for FPGAs Using Shannon s ExpansionDeshanand P. Singh, Stephen Dean Brown. vlsi 2003: 41-50

2002

Constrained clock shifting for field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. fpga 2002: 121-126 [doi]

Incremental placement for layout driven optimizations on FPGAsDeshanand P. Singh, Stephen Dean Brown. iccad 2002: 752-759 [doi]

Integrated retiming and placement for field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. fpga 2002: 67-76 [doi]

2001

The case for registered routing switches in field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. fpga 2001: 161-169 [doi]

Sign in or sign up to see more results.

runs on WebDSL