Dipankar Sarkar - researchr alias

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Viewing Publication 1 - 45 from 45

2021

An Intrusion Detection System Using Modified-Firefly Algorithm in Cloud EnvironmentPartha Ghosh, Dipankar Sarkar, Joy Sharma, Santanu Phadikar. ijdcf, 13(2):77-93, 2021. [doi]

2019

SamaTulyataOne: A Path Based Equivalence CheckerSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal. indiaSE 2019: [doi]

Equivalence checking of Petri net models of programs using static and dynamic cut-pointsSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal 0001. ACTA, 56(4):321-383, 2019. [doi]

Verification of parallelising transformations of KPN modelsChandan Karfa, Dipankar Sarkar, Chittaranjan Mandal 0001. iet-cps, 4(3):276-289, 2019. [doi]

2017

2016

An efficient path based equivalence checking for Petri net based models of programsSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal. indiaSE 2016: 70-79 [doi]

A Path Construction Algorithm for Translation Validation Using PRES+ ModelsSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu. ppl, 26(2):1-25, 2016. [doi]

Translation validation of loop and arithmetic transformations in the presence of recurrencesKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. lctrts 2016: 31-40 [doi]

An Enhanced Equivalence Checking Method to Handle Bugs in Programs with RecurrencesSudakshina Dutta, Dipankar Sarkar. ENASE 2016: 254-259 [doi]

Validation of Loop Parallelization and Loop Vectorization TransformationsSudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh. ENASE 2016: 195-202 [doi]

2015

A Path-based Equivalence Checking Method for Petri Net based Models of ProgramsSoumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal. ICSOFT 2015: 319-329 [doi]

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of ProgramsSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal. ICSE 2015: 827-828 [doi]

Validating SPARK: High Level Synthesis CompilerSoumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal. isvlsi 2015: 195-198 [doi]

Translation Validation of Transformations of Embedded System Specifications Using Equivalence CheckingKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. isvlsi 2015: 183-186 [doi]

A translation validation framework for symbolic value propagation based equivalence checking of FSMDAsKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. SCAM 2015: 247-252 [doi]

2014

Extending the FSMD Framework for Validating Code Motions of Array-Handling ProgramsKunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal. tcad, 33(12):2015-2019, 2014. [doi]

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solversKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. vdat 2014: 1-6 [doi]

Verification of Code Motion Techniques Using Value PropagationKunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal. tcad, 33(8):1180-1193, 2014. [doi]

2013

A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded SystemsSoumyajit Dey, Dipankar Sarkar, Anupam Basu. TC, 62(10):1917-1931, 2013. [doi]

Verification of KPN Level TransformationsChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal. vlsid 2013: 338-343 [doi]

Verification of Loop and Arithmetic Transformations of Array-Intensive BehaviorsChandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal. tcad, 32(11):1787-1800, 2013. [doi]

2012

2011

2010

Fairness of Transitions in Diagnosability of Discrete Event SystemsSantosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra. deds, 20(3):349-376, 2010. [doi]

Diagnosability of delay-deadline failures in fair real time discrete event modelsSantosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay. ijsysc, 41(7):763-782, 2010. [doi]

A Tag Machine Based Performance Evaluation Method for Job-Shop SchedulesSoumyajit Dey, Dipankar Sarkar, Anupam Basu. tcad, 29(7):1028-1041, 2010. [doi]

Data-Flow Driven Equivalence Checking for Verification of Code Motion TechniquesChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal. isvlsi 2010: 428-433 [doi]

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital CircuitsChandan Karfa, Dipankar Sarkar, Chitta Mandal. tcad, 29(3):479-492, 2010. [doi]

2008

An Equivalence-Checking Method for Scheduling Verification in High-Level SynthesisChandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar. tcad, 27(3):556-569, 2008. [doi]

2007

2006

A Formal Verification Method of Scheduling in High-level SynthesisChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. isqed 2006: 71-78 [doi]

Verification of Scheduling in High-level SynthesisChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. isvlsi 2006: 141-146 [doi]

2004

Model checking on state transition diagramBatsayan Das, Dipankar Sarkar, Santanu Chattopadhyay. aspdac 2004: 412-417 [doi]

2000

Status Condition Analysis during Data Path Verification of Sequential CircuitsDipankar Sarkar. vlsid 2000: 70-75 [doi]

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