Farid N. Najm - researchr alias

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2011

Fast Vectorless Power Grid Verification Under an RLC ModelNahi H. Abdul Ghani, Farid N. Najm. tcad, 30(5):691-703, 2011. [doi]

2010

2009

Low-Power Programmable FPGA Routing CircuitryJason Helge Anderson, Farid N. Najm. tvlsi, 17(8):1048-1060, 2009. [doi]

Fast vectorless power grid verification using an approximate inverse techniqueNahi H. Abdul Ghani, Farid N. Najm. dac 2009: 184-189 [doi]

Full-Chip Model for Leakage-Current Estimation Considering Within-Die CorrelationKhaled R. Heloue, Navid Azizi, Farid N. Najm. tcad, 28(6):874-887, 2009. [doi]

Quantifying robustness metrics in parameterized static timing analysisKhaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm. iccad 2009: 209-216 [doi]

Clock skew optimization via wiresizing for timing sign-off covering all process cornersSari Onaissi, Khaled R. Heloue, Farid N. Najm. dac 2009: 196-201 [doi]

PSTA-based branch and bound approach to the silicon speedpath isolation problemSari Onaissi, Khaled R. Heloue, Farid N. Najm. iccad 2009: 217-224 [doi]

2008

2007

Variations-Aware Low-Power Design and Block Clustering With Voltage ScalingNavid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm. tvlsi, 15(7):746-757, 2007. [doi]

Early power grid verification under circuit current uncertaintiesImad A. Ferzli, Farid N. Najm, Lars Kruse. islped 2007: 116-121 [doi]

A geometric approach for early power grid verification using current constraintsImad A. Ferzli, Farid N. Najm, Lars Kruse. iccad 2007: 40-47 [doi]

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die CorrelationKhaled R. Heloue, Navid Azizi, Farid N. Najm. dac 2007: 93-98 [doi]

Maximum circuit activity estimation using pseudo-boolean satisfiabilityHratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir. date 2007: 1538-1543 [doi]

A Yield Model for Integrated Circuits and its Application to Statistical Timing AnalysisFarid N. Najm, Noel Menezes, Imad A. Ferzli. tcad, 26(3):574-591, 2007. [doi]

2006

Active leakage power optimization for FPGAsJason Helge Anderson, Farid N. Najm. tcad, 25(3):423-437, 2006. [doi]

A family of cells to reduce the soft-error-rate in ternary-CAMNavid Azizi, Farid N. Najm. dac 2006: 779-784 [doi]

High-level current macro model for logic blocksSrinivas Bodapati, Farid N. Najm. tcad, 25(5):837-855, 2006. [doi]

Analysis and verification of power grids considering process-induced leakage-current variationsImad A. Ferzli, Farid N. Najm. tcad, 25(1):126-143, 2006. [doi]

Handling inductance in early power grid verificationNahi H. Abdul Ghani, Farid N. Najm. iccad 2006: 127-134 [doi]

Voltage-Aware Static Timing AnalysisDionysios Kouroussis, Rubil Ahmadi, Farid N. Najm. tcad, 25(10):2156-2169, 2006. [doi]

An adaptive FPGA architecture with process variation compensation and reduced leakageGeorges Nabaa, Navid Azizi, Farid N. Najm. dac 2006: 624-629 [doi]

A linear-time approach for static timing analysis covering all process cornersSari Onaissi, Farid N. Najm. iccad 2006: 217-224 [doi]

Dynamic-range estimationBin Wu, Jianwen Zhu, Farid N. Najm. tcad, 25(9):1618-1636, 2006. [doi]

2005

Variations-aware low-power design with voltage scalingNavid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm. dac 2005: 529-534 [doi]

Leakage power: trends, analysis and avoidanceDavid Blaauw, Anirudh Devgan, Farid N. Najm. aspdac 2005: [doi]

Early power estimation for VLSI circuitsKavel M. Büyüksahin, Farid N. Najm. tcad, 24(7):1076-1088, 2005. [doi]

Statistical timing analysis with two-sided constraintsKhaled R. Heloue, Farid N. Najm. iccad 2005: 829-836

Incremental partitioning-based vectorless power grid verificationDionysios Kouroussis, Imad A. Ferzli, Farid N. Najm. iccad 2005: 358-364

A Case for Asymmetric-Cell Cache MemoriesAndreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi. tvlsi, 13(7):877-881, 2005. [doi]

On the need for statistical timing analysisFarid N. Najm. dac 2005: 764-765 [doi]

Power grid voltage integrity verificationMaha Nizam, Farid N. Najm, Anirudh Devgan. islped 2005: 239-244 [doi]

A non-parametric approach for dynamic range estimation of nonlinear systemsBin Wu, Jianwen Zhu, Farid N. Najm. dac 2005: 841-844 [doi]

2004

Interconnect capacitance estimation for FPGAsJason Helge Anderson, Farid N. Najm. aspdac 2004: 713-718 [doi]

Power estimation techniques for FPGAsJason Helge Anderson, Farid N. Najm. tvlsi, 12(10):1015-1027, 2004. [doi]

Active leakage power optimization for FPGAsJason Helge Anderson, Farid N. Najm, Tim Tuan. fpga 2004: 33-41 [doi]

Low-power programmable routing circuitry for FPGAsJason Helge Anderson, Farid N. Najm. iccad 2004: 602-609 [doi]

An Asymmetric SRAM Cell to Lower Gate LeakageNavid Azizi, Farid N. Najm. isqed 2004: 534-539 [doi]

Worst-case circuit delay taking into account power supply variationsDionysios Kouroussis, Rubil Ahmadi, Farid N. Najm. dac 2004: 652-657 [doi]

Statistical timing analysis based on a timing yield modelFarid N. Najm, Noel Menezes. dac 2004: 460-465 [doi]

Dynamic range estimation for nonlinear systemsBin Wu, Jianwen Zhu, Farid N. Najm. iccad 2004: 660-667 [doi]

An analytical approach for dynamic range estimationBin Wu, Jianwen Zhu, Farid N. Najm. dac 2004: 472-477 [doi]

2003

Timing Analysis in Presence of Power Supply and Ground Voltage VariationsRubil Ahmadi, Farid N. Najm. iccad 2003: 176-183 [doi]

Switching activity analysis and pre-layout activity prediction for FPGAsJason Helge Anderson, Farid N. Najm. slip 2003: 15-21 [doi]

Low-leakage asymmetric-cell SRAMNavid Azizi, Farid N. Najm, Andreas Moshovos. tvlsi, 11(4):701-715, 2003. [doi]

ESTIMA: an architectural-level power estimator for multi-ported pipelined register filesKavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm. islped 2003: 294-297 [doi]

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variationsImad A. Ferzli, Farid N. Najm. dac 2003: 856-859 [doi]

Statistical Verification of Power Grids Considering Process-Induced Leakage Current VariationsImad A. Ferzli, Farid N. Najm. iccad 2003: 770-777 [doi]

Design Techniques for Gate-Leakage Reduction in CMOS CircuitsRafik S. Guindi, Farid N. Najm. isqed 2003: 61 [doi]

Energy and peak-current per-cycle estimation at RTLSubodh Gupta, Farid N. Najm. tvlsi, 11(4):525-537, 2003. [doi]

A static pattern-independent technique for power grid voltage integrity verificationDionysios Kouroussis, Farid N. Najm. dac 2003: 99-104 [doi]

2002

2001

Frequency-domain supply current macro-modelSrinivas Bodapati, Farid N. Najm. islped 2001: 295-298 [doi]

Power estimation for large sequential circuitsJoseph N. Kozhaya, Farid N. Najm. tvlsi, 9(2):400-407, 2001. [doi]

Multigrid-Like Technique for Power Grid AnalysisJoseph N. Kozhaya, Sani R. Nassif, Farid N. Najm. iccad 2001: 480-487 [doi]

2000

1999

1998

Delay Estimation VLSI Circuits from a High-Level ViewMahadevamurty Nemani, Farid N. Najm. dac 1998: 591-594 [doi]

1997

1996

Towards a high-level power estimation capability [digital ICs]Mahadevamurty Nemani, Farid N. Najm. tcad, 15(6):588-598, 1996. [doi]

High-level power estimation and the area complexity of Boolean functionsMahadevamurty Nemani, Farid N. Najm. islped 1996: 329-334 [doi]

1995

1994

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI CircuitsHarish Kriplani, Farid N. Najm, Ibrahim N. Hajj. iscas 1994: 435-438

Low-pass filter for computing the transition density in digital circuitsFarid N. Najm. tcad, 13(9):1123-1131, 1994. [doi]

A survey of power estimation techniques in VLSI circuitsFarid N. Najm. tvlsi, 2(4):446-455, 1994. [doi]

Statistical Estimation of the Switching Activity in Digital CircuitsMichael G. Xakellis, Farid N. Najm. dac 1994: 728-733 [doi]

1993

A Monte Carlo approach for power estimationRichard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick. tvlsi, 1(1):63-71, 1993. [doi]

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational CircuitsHarish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj. dac 1993: 384-388 [doi]

Transition density: a new measure of activity in digital circuitsFarid N. Najm. tcad, 12(2):310-323, 1993. [doi]

1992

McPOWER: a Monte Carlo approach to power estimationRichard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick. iccad 1992: 90-97 [doi]

Maximum Current Estimation in CMOS CircuitsHarish Kriplani, Farid N. Najm, Ibrahim N. Hajj. dac 1992: 2-7 [doi]

1991

Transition Density, A Stochastic Measure of Activity in Digital CircuitsFarid N. Najm. dac 1991: 644-649 [doi]

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