Gerald E. Sobelman - researchr alias

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2011

2010

Frequency domain adaptive tap partial update adaptive algorithm for network echo cancellationJie Yang, Gerald E. Sobelman. icassp 2010: 4046-4049 [doi]

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband PlatformShuang Zhao, Wenqing Lu, Xiaofang Zhou, Dian Zhou, Gerald E. Sobelman. ieicet, 93-D(4):811-821, 2010. [doi]

2009

Mesh-star Hybrid NoC Architecture with CDMA SwitchWoojoon Lee, Gerald E. Sobelman. iscas 2009: 1349-1352 [doi]

Gradient-based target localization in robotic sensor networksQingquan Zhang, Gerald E. Sobelman, Tian He. percom, 5(1):37-48, 2009. [doi]

2008

2007

High Speed Look-Ahead LMS Detector for MIMO SystemsWen-Chih Kan, Gerald E. Sobelman. sips 2007: 56-60 [doi]

MIMO Transceiver Design Based on a Modified Geometric Mean DecompositionWen-Chih Kan, Gerald E. Sobelman. iscas 2007: 677-680 [doi]

2006

Noise Model Analysis of Optimized Mixed-Radix Structures for Pulsed OFDMKai-Chuan Chang, Gerald E. Sobelman. globecom 2006: [doi]

FPGA-Based Design of a Pulsed-OFDM SystemKai-Chuan Chang, Gerald E. Sobelman. apccas 2006: 1128-1131 [doi]

Modeling and verification of high-speed wired links with Verilog-AMSMing-Ta Hsieh, Gerald E. Sobelman. iscas 2006: [doi]

DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCsDaewook Kim, Manho Kim, Gerald E. Sobelman. iscas 2006: [doi]

Network-on-chip quality-of-service through multiprotocol label switchingManho Kim, Daewook Kim, Gerald E. Sobelman. iscas 2006: [doi]

NIUGAP: low latency network interface architecture with Gray code for networks-on-chipDaewook Kim, Manho Kim, Gerald E. Sobelman. iscas 2006: [doi]

Network-on-chip link analysis under power and performance constraintsManho Kim, Daewook Kim, Gerald E. Sobelman. iscas 2006: [doi]

Low-Power Bus Transform Coding for Multilevel SignalsFakhrul Zaman Rokhani, Gerald E. Sobelman. apccas 2006: 1272-1275 [doi]

Implementation of a Multi-band Pulsed-OFDM TransceiverEbrahim Saberinia, K. C. Chang, Gerald E. Sobelman, Ahmed H. Tewfik. vlsisp, 43(1):73-88, 2006. [doi]

TwinsNet: A Cooperative MIMO Mobile Sensor NetworkQingquan Zhang, Woong Cho, Gerald E. Sobelman, Liuqing Yang, Richard M. Voyles. uic 2006: 508-516 [doi]

Gradient-Driven Target Acquisition in Mobile Wireless Sensor NetworksQingquan Zhang, Gerald E. Sobelman, Tian He. dmsn 2006: 365-376 [doi]

2005

Clock and data recovery with adaptive loop gain for spread spectrum SerDes applicationsMing-Ta Hsieh, Gerald E. Sobelman. iscas 2005: 4883-4886 [doi]

Parallel FFT computation with a CDMA-based network-on-chipDaewook Kim, Manho Kim, Gerald E. Sobelman. iscas 2005: 1138-1141 [doi]

FPGA-Based CDMA Switch for Networks-on-ChipDaewook Kim, Manho Kim, Gerald E. Sobelman. fccm 2005: 283-284 [doi]

2004

2002

High-speed add-compare-select units using locally self-resetting CMOSGunok Jung, Jun Jin Kong, Gerald E. Sobelman, Keshab K. Parhi. iscas 2002: 889-892 [doi]

A robust self-resetting CMOS 32-bit parallel adderGunok Jung, V. A. Sundarajan, Gerald E. Sobelman. iscas 2002: 473-476 [doi]

Efficient digit-serial FIR filters with skew-tolerant dominoSungwook Kim, Gerald E. Sobelman. iscas 2002: 369-372 [doi]

1999

Elliptic Curve Scalar Multiplier Design Using FPGAsLijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman. ches 1999: 257-268 [doi]

A Compact Fast Variable Key Size Elliptic Curve Cryptosystem CoprocessorLijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman. fccm 1999: 304-305 [doi]

1998

Digit-Serial DSP Library for Optimized FPGA ConfigurationHanho Lee, Gerald E. Sobelman. fccm 1998: 322-323 [doi]

FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract)Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman. fpga 1998: 257 [doi]

1997

A New Low-Voltage Full Adder CircuitHanho Lee, Gerald E. Sobelman. glvlsi 1997: 88 [doi]

1995

Low-Power Multiplier Design Using Delayed EvaluationGerald E. Sobelman, Donovan L. Raatz. iscas 1995: 1564-1567

1993

A programmable floating-point cell for systolic signal processingRoss Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken. vlsisp, 5(1):75-83, 1993. [doi]

1991

Simulation-based design of programmable systolic arraysRob Smith, Gerald E. Sobelman. cad, 23(10):669-675, 1991. [doi]

A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor FaultsE. Vandris, Gerald E. Sobelman. itc 1991: 608-614

Algorithms for Fast, Memory Efficient Switch-Level Fault SimulationE. Vandris, Gerald E. Sobelman. dac 1991: 138-143 [doi]

1990

Fast Switch-Level Fault Simulation Using Functional Fault ModelingE. Vandris, Gerald E. Sobelman. iccad 1990: 74-77

1986

Automated layout synthesis in the YASC silicon compilerDavid E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin. dac 1986: 447-453 [doi]

1985

Yet another silicon compilerDavid E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon. dac 1985: 176-182 [doi]

1984

A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and ModelingO. Melstrand, Eamonn O Neill, Gerald E. Sobelman, D. Dokos. tcad, 3(1):47-51, 1984. [doi]