Hideharu Amano - researchr alias

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2011

A Switch-Tagged Routing Methodology for PC Clusters with VLAN EthernetMichihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano. tpds, 22(2):217-230, 2011. [doi]

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. tcad, 30(4):520-533, 2011. [doi]

A vertical bubble flow network using inductive-coupling for 3-D CMPsHiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano. nocs 2011: 49-56 [doi]

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple PredictorsHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga. TC, 60(6):783-799, 2011. [doi]

An analytical network performance model for SIMD processor CSX600 interconnectsYuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano. jsa, 57(1):146-159, 2011. [doi]

On-chip detection methodology for break-even time of power gated function unitsKimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura. islped 2010: 241-246 [doi]

Dynamic V::DD:: Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy ReductionTatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami. arc 2011: 230-241 [doi]

A Leakage Efficient Data TLB Design for Embedded ProcessorsLei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano. ieicet, 94-D(1):51-59, 2011. [doi]

2010

Stabilizing Path Modification of Power-Aware On/Off Interconnection NetworksJose Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano. NAS 2010: 218-227 [doi]

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration MappingKazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano. fpt 2010: 349-352 [doi]

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gatingDaisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo. aspdac 2010: 369-370 [doi]

Reducing instruction TLB s leakage power consumption for embedded processorsZhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki. green 2010: 477-484 [doi]

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPsHiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. nocs 2010: 61-68 [doi]

Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA systemHirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. sigarch, 38(4):8-13, 2010. [doi]

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through SwitchingYuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano. NAS 2010: 431-438 [doi]

A datapath classification method for FPGA-based scientific application accelerator systemsYui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri. fpt 2010: 441-444 [doi]

MuCCRA-3: a low power dynamically reconfigurable processor arrayYoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano. aspdac 2010: 377-378 [doi]

Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. ProceedingsPhaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano, editors, Volume 5992 of Lecture Notes in Computer Science, Springer, 2010. [doi]

Wire congestion aware synthesis for a dynamically reconfigurable processorTakao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano. fpt 2010: 300-303 [doi]

Adaptive power gating for function units in a microprocessorKimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. isqed 2010: 29-37 [doi]

A Performance Evaluation of CUBE: One-Dimensional 512 FPGA ClusterMasato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer. arc 2010: 372-381 [doi]

2009

An On/Off Link Activation Method for Power Regulation in InfiniBandJose Miguel Montanana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano. pdpta 2009: 289-295

Balanced Dimension-Order Routing for k-ary n-cubesJose Miguel Montanana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano. icppw 2009: 499-506 [doi]

Guest Editors Introduction: ICFPT 2007Hideharu Amano, Tadao Nakamura. trets, 2(2), 2009. [doi]

Japanese Dynamically Reconfigurable ProcessorsHideharu Amano. ersa 2009: 19-28

Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAsKenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. fpl 2009: 654-657 [doi]

Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical SimulatorTomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri. arc 2009: 368-373 [doi]

An on/off link activation method for low-power ethernet in PC clustersMichihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano. ipps 2009: 1-11 [doi]

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip NetworkHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano. tpds, 20(8):1126-1141, 2009. [doi]

Prediction router: Yet another low latency on-chip router architectureHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga. hpca 2009: 367-378 [doi]

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulatorTomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano. fpl 2009: 679-682 [doi]

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor ArrayYoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano. ersa 2009: 283-286

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling linkShotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano. fpl 2009: 6-11 [doi]

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable ProcessorsToru Sano, Yoshiki Saito, Hideharu Amano. ersa 2009: 112-118

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable ProcessorsToru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano. fpl 2009: 530-533 [doi]

Code Compression with Split Echo InstructionsIver Stubdal, Arda Karaduman, Hideharu Amano. ieicet, 92-D(9):1650-1656, 2009. [doi]

Evaluation of a multicore reconfigurable architecture with variable core sizesVu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano. ipps 2009: 1-8 [doi]

Design and Implementation of Fine-Grain Power Gating with Ground Bounce SuppressionKimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura. vlsid 2009: 381-386 [doi]

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAsDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ieicet, 92-D(4):575-583, 2009. [doi]

A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGAHideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri. reconfig 2009: 125-130 [doi]

Cache Controller Design on Ultra Low Leakage Embedded ProcessorsLei Zhao, Hui Xu, Naomi Seki, Saito Yoshiki, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano. arcs 2009: 171-182 [doi]

2008

Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEsMasaru Kato, Yohei Hasegawa, Hideharu Amano. ersa 2008: 215-221

Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable ProcessorYuken Kishimoto, Shinichiro Haruyama, Hideharu Amano. reconfig 2008: 247-252 [doi]

A Lightweight Fault-Tolerant Mechanism for Network-on-ChipMichihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston. nocs 2008: 13-22 [doi]

Adding Slow-Silent Virtual Channels for Low-Power On-Chip NetworksHiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano. nocs 2008: 23-32 [doi]

Run-time power gating of on-chip routers using look-ahead routingHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang. aspdac 2008: 55-60 [doi]

Three-Dimensional Layout of On-Chip Tree-Based NetworksHiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano. ispan 2008: 281-288 [doi]

Power reduction techniques for Dynamically Reconfigurable Processor ArraysTakashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano. fpl 2008: 305-310 [doi]

Instruction buffer mode for multi-context Dynamically Reconfigurable ProcessorsToru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano. fpl 2008: 215-220 [doi]

A Method for Capturing State Data on Dynamically Reconfigurable ProcessorsVu Manh Tuan, Hideharu Amano. ersa 2008: 208-214

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable ProcessorVu Manh Tuan, Hideharu Amano. arc 2008: 171-182 [doi]

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable ProcessorsVu Manh Tuan, Hideharu Amano. ieicet, 91-D(12):2793-2803, 2008. [doi]

A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor ArraysVasutan Tunbunheng, Hideharu Amano. ieicet, 91-D(11):2655-2665, 2008. [doi]

A link removal methodology for Networks-on-Chip on reconfigurable systemsDaihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi. fpl 2008: 269-274 [doi]

Practical implementation of a network-based stochastic biochemical simulation system on an FPGAMasato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano. fpl 2008: 663-666 [doi]

2007

Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor ArraysYohei Hasegawa, Hideharu Amano. fpl 2007: 796-799 [doi]

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular NetworksAkiya Jouraku, Michihiro Koibuchi, Hideharu Amano. tpds, 18(3):320-333, 2007. [doi]

Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGATakamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka. IEEEcit 2007: 567-572 [doi]

A High Speed License Plate Recognition System on an FPGATakamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka. fpl 2007: 554-557 [doi]

Performance evaluation on low-latency communication mechanism of DIMMnet-2Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano. pdcn 2007: 57-62

Tightly-Coupled Multi-Layer Topologies for 3-D NoCsHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. icpp 2007: 75 [doi]

Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip NetworkHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ipps 2007: 1-10 [doi]

Performance Improvement Methodology for ClearSpeed s CSX600Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano. icpp 2007: 77 [doi]

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory SlotAtushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo. pdpta 2007: 787-793

Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable ProcessorVu Manh Tuan, Yohei Hasegawa, Hideharu Amano. ersa 2007: 203-206

Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable DevicesVasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano. ieicet, 90-D(2):473-481, 2007. [doi]

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAsDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ieicet, 90-D(12):1914-1922, 2007. [doi]

A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable SystemsDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. fpl 2007: 383-388 [doi]

Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCsKonosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano. tpds, 18(9):1282-1295, 2007. [doi]

A Combining technique of rate law functions for a cost-effective reconfigurable biological simulatorHideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri. fpl 2007: 808-811 [doi]

FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction MethodMasato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano. fpl 2007: 254-259 [doi]

2006

A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable ProcessorsHideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura. fpl 2006: 1-6 [doi]

A Survey on Dynamically Reconfigurable ProcessorsHideharu Amano. ieicet, 89-B(12):3179-3187, 2006. [doi]

A Simple Data Transfer Technique Using Local Address for Networks-on-ChipsMichihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano. tpds, 17(12):1425-1437, 2006. [doi]

A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus NetworksHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ISCApdcs 2006: 24-31

Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual ChannelsHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ispa 2006: 207-218 [doi]

Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSipYasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. fpl 2006: 1-6 [doi]

Switch-tagged VLAN Routing Methodology for PC Clusters with EthernetTomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano. icpp 2006: 479-486 [doi]

A cost-effective context memory structure for dynamically reconfigurable processorsMasayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano. ipps 2006: [doi]

Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable ProcessorVu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano. arc 2006: 115-121 [doi]

A Parametric Study of Scalable Interconnects on FPGAsDaihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano. ersa 2006: 130-135

An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical SystemsMasato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. fpl 2006: 1-6 [doi]

2005

An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa. fpl 2005: 347-352

Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable ProcessorKatsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano. arcs 2005: 12-18

A Packet Forwarding Layer for DIMMnet and its Hardware ImplementationYoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo. pdpta 2005: 461-467

Implementation of ISIS-SimpleScalarToshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano. pdpta 2005: 117-123

An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable ProcessorYohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima. fpt 2005: 163-170

Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluationYohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano. fpga 2005: 265 [doi]

Evaluation of Network Interface Controller on DIMMnet-2 Prototype BoardAkira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo. pdcat 2005: 778-780 [doi]

Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 ClusterMichihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano. tpds, 16(8):747-759, 2005. [doi]

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive RoutingMichihiro Koibuchi, Akiya Jouraku, Hideharu Amano. ieicet, 88-D(1):109-118, 2005. [doi]

Path selection algorithm: the strategy for designing deterministic routing from alternative pathsMichihiro Koibuchi, Akiya Jouraku, Hideharu Amano. pc, 31(1):117-130, 2005. [doi]

Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-ChipsHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. pdpta 2005: 1343-1349

Non-Minimal Routing Strategy for Application-Specific Networks-on-ChipsHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano. icppw 2005: 273-280 [doi]

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano. pc, 31(3-4):352-370, 2005. [doi]

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano. ishpc 2008: 211-218 [doi]

A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGAYasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. fpl 2005: 574-577

RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable DevicesVasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano. fpt 2005: 129-136

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