Hideki Asai - researchr alias

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Viewing Publication 1 - 74 from 74

2022

2020

A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton MethodS. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai. iscas 2020: 1 [doi]

2019

2018

Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on TensorflowS. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai. icmla 2018: 1147-1154 [doi]

2017

SI/PI/EMI simulation techniques and application to automotive electronic design issuesHideki Asai. mixdes 2017: 41-44 [doi]

2014

ForewordHideki Asai. ieicet, 97-A(3):725, 2014. [doi]

HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission linesTakahiro Takasaki, Tadatoshi Sekine, Hideki Asai. aspdac 2014: 774-779 [doi]

2013

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon viaTadatoshi Sekine, Hideki Asai. aspdac 2013: 7-12 [doi]

2012

Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuitsHiroki Kurobe, Tadatoshi Sekine, Hideki Asai. aspdac 2012: 365-370 [doi]

2010

2009

CMOS Circuit Simulation Using Latency Insertion MethodTadatoshi Sekine, Hideki Asai. ieicet, 92-A(10):2546-2553, 2009. [doi]

2008

2007

Application of Relaxation-Based Technique to ADI-FDTD Method and Its EstimationYuya Nakazono, Hideki Asai. iscas 2007: 1489-1492 [doi]

A fast transient simulation based on Model Order Reduction and RLCG-MNA formulationAkira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai. ecctd 2007: 775-778 [doi]

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog AlgorithmTakayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai. ieicet, 90-A(2):388-397, 2007. [doi]

2006

An Enhanced Time-Domain Circuit Simulation Technique Based on LIMHidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai. ieicet, 89-A(5):1505-1506, 2006. [doi]

Two-staged Tabu Search for Floorplan Problem Using O-Tree RepresentationHiroshi Ninomiya, Kimihiko Numayama, Hideki Asai. cec 2006: 718-724 [doi]

Large scale RLC circuit analysis using RLCG-MNA formulationYuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai. date 2006: 45-46 [doi]

Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA FormulationYuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai. isqed 2006: 393-400 [doi]

Fast timing analysis of plane circuits via two-layer CNN-based modelingYuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida. iscas 2006: [doi]

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parametersTakayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai. aspdac 2006: 832-837 [doi]

Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-AT. Yamamoto, T. Suzuki, Hideki Asai. cicc 2006: 341-344 [doi]

2005

Generalized method of the time-domain circuit simulation based on LIM with MNA formulationHidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai. cicc 2005: 289-292 [doi]

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuitsTakashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. iscas 2005: 4903-4906 [doi]

Interconnect simulation using FDTD method with variable mesh size techniqueHirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai. ecctd 2005: 225-228 [doi]

New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled DataYuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai. ieicet, 88-A(2):524-532, 2005. [doi]

Optimization procedure of class E amplifiers using SPICEYuichi Tanji, Hiroo Sekiya, Hideki Asai. ecctd 2005: 133-136 [doi]

Modeling of power distribution networks with signal lines for SPICE simulatorsTakayuki Watanabe, Hideki Asai. iscas 2005: 5774-5777 [doi]

Three dimensional module packing by simulated annealingHirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai. cec 2005: 1069-1074 [doi]

2004

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed CircuitsTakashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. date 2004: 1327-1333 [doi]

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effectsYuichi Tanji, Hideki Asai. dac 2004: 810-813 [doi]

2003

Behavioral modeling of EM devices by selective orthogonal matrix least-squares methodYuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai. aspdac 2003: 184-188 [doi]

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance ValuesShashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai. ieiceta, 86-A(2):335-341, 2003. [doi]

Analysis of PCB interconnects using electromagnetic reduction techniqueTakayuki Watanabe, Hideki Asai. iscas 2003: 498-501 [doi]

A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic RadiationsTakayuki Watanabe, Hideki Asai. ieiceta, 86-A(2):252-261, 2003. [doi]

Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural NetworkMasahiro Yoshida, Takeshi Kamio, Hideki Asai. ieiceta, 86-A(10):2623-2627, 2003. [doi]

2002

2001

A Neuro-Based Optimization Algorithm for Tiling Problems with RotationShinsuke Manabe, Hideki Asai. npl, 13(3):267-275, 2001.

High-speed interconnect simulation using MIMO type of adaptive least square methodMasaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai. iscas 2001: 327-330 [doi]

2000

Design Method of Limit Cycle Generator by Hysteresis Neural NetworksTeru Yoneyama, Hideki Asai, Hiroshi Ninomiya. ijcnn 2000: 500-505 [doi]

Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh TransformMasahiro Yoshida, Hideki Asai, Takeshi Kamio. ijcnn 2000: 315-319 [doi]

1999

A neuro-based optimization algorithm for tiling problems with rotationShinsuke Manabe, Hideki Asai. ijcnn 1999: 3750-3753 [doi]

Design method of neural networks for limit cycle generatorTeru Yoneyama, Hiroshi Ninomiya, Hideki Asai. ijcnn 1999: 2402-2405 [doi]

1998

Neural network simulator for spatiotemporal pattern analysisAtsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai. icecsys 1998: 109-112 [doi]

SPADE : analog/digital mixed signal simulator with analog hardware description languageHiroshi Sagesaka, Hisashi Irii, Hideki Asai. icecsys 1998: 517-520 [doi]

Transient analysis for high-speed interconnect networks based on AWE and delay evaluation techniqueTakayuki Watanabe, Hideki Asai. icecsys 1998: 103-106 [doi]

1997

Application of neuro-based optimization algorithm to three dimensional cylindric puzzlesHiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai. icnn 1997: 1246-1250 [doi]

1996

1995

1994

1987

Special parallel processor for lu decomposition of a large-scale sparse matrixHideki Asai, Mitsuo Asai, Mamoru Tanaka. scjapan, 18(6):89-99, 1987. [doi]

1985

Network analysis by hierarchical tearing methodHideki Asai, Shinsaku Mori. scjapan, 16(6):59-67, 1985. [doi]

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