Hiroshi Makino - researchr alias

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Viewing Publication 1 - 43 from 43

2016

2015

The Challenge of Collaboration among Academies and Asia Pacific for ITS R&DHiroshi Makino, Shunsuke Kamijo. ieicet, 98-A(1):259-266, 2015. [doi]

2014

Development of the SCARAHiroshi Makino. jrm, 26(1):5-8, 2014. [doi]

The LSI implementation of a memory based field programmable device for MCU peripheralsTetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda. ddecs 2014: 183-188 [doi]

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line VoltageShunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda. tvlsi, 22(3):686-690, 2014. [doi]

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty RatioShunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. tcas, 61-I(7):2194-2203, 2014. [doi]

A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitanceShunji Nakata, Hiroshi Makino, Yoshio Matsuda. mwscas 2014: 439-442 [doi]

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor CurrentShunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda. jcsc, 23(3), 2014. [doi]

2013

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked LoopTsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda. tcas, 60-I(4):896-907, 2013. [doi]

2012

2011

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the DistributionHiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. tcas, 58-II(4):230-234, 2011. [doi]

2010

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipationShunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda. ieiceee, 7(9):640-646, 2010. [doi]

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuitShunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda. iscas 2010: 2474-2477 [doi]

2009

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-AccessKoji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara. jssc, 44(3):977-986, 2009. [doi]

2008

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access IssuesSatoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu. jssc, 43(4):938-945, 2008. [doi]

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature VariationsKoji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara. jssc, 43(1):180-191, 2008. [doi]

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technologyHiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara. islped 2008: 15-20 [doi]

2007

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCsMitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata. isscc 2007: 288-603 [doi]

Research and Commercialization of SCARA Robot -The Case of Industry-University Joint Research and Development-Hiroshi Makino, Akitaka Kato, Yasunori Yamazaki. ijat, 1(1):61-67, 2007. [doi]

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing CircuitsShigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara. jssc, 42(4):820-829, 2007. [doi]

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature VariationsMakoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara. isscc 2007: 326-606 [doi]

2005

2004

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applicationsKoji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade. jssc, 39(4):684-693, 2004. [doi]

2001

A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace treeNiichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba. jssc, 36(2):249-257, 2001. [doi]

1998

Robot contest "Robocon Yamanashi"Noriaki Kiyohiro, Hiroshi Makino, Hideo Mori. jrm, 10(1):34-39, 1998. [doi]

A low power SRAM using auto-backgate-controlled MT-CMOSKoji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano. islped 1998: 293-298 [doi]

1997

1996

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architectureHiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. jssc, 31(6):773-783, 1996. [doi]

1995

A BiCMOS wired-OR logicYasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko. jssc, 30(6):622-628, June 1995. [doi]

1993

A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary ArchitectureHiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara. iccd 1993: 202-205

1989

Development of the Spherical SCARA RobotHiroshi Makino. jrm, 1(3):251-252, 1989. [doi]

1985

Beta: An Automatic Kana-Kanji Translation SystemHiroshi Makino. Computer, 18(1):46-52, 1985. [doi]

1980

An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana SentencesHiroshi Makino, Makoto Kizawa. COLING 1980: 295-302 [doi]

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