Hubert Kaeslin - researchr alias

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Viewing Publication 1 - 51 from 51

2018

Towards Edge-Aware Spatio-Temporal Filtering in Real-TimeMichael Schaffner, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic. TIP, 27(1):265-280, 2018. [doi]

2016

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDWMichael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic. tcsv, 26(11):2093-2108, 2016. [doi]

2015

Semiconductor Technology and the Energy Efficiency of ICTHubert Kaeslin. In Lorenz M. Hilty, Bernard Aebischer, editors, ICT Innovations for Sustainability. Volume 310 of Advances in Intelligent Systems and Computing, pages 105-111, Springer, 2015. [doi]

Automatic multiview synthesis - Towards a mobile system on a chipMichael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic. vcip 2015: 1-4 [doi]

Automatic multiview synthesis - Prototype demoMichael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic. vcip 2015: 1 [doi]

2014

2013

Live demonstration: Real-time audio restoration using sparse signal recoveryDavid E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer. iscas 2013: 659 [doi]

Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing ApplicationsPierre Greisen, Marian Runo, Patrice Guillet, Simon Heinzle, Aljoscha Smolic, Hubert Kaeslin, Markus H. Gross. tcsv, 23(8):1402-1407, 2013. [doi]

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warpingMichael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic. esscirc 2013: 61-64 [doi]

A real-time 720p feature extraction core based on Semantic Kernels BinarizedMichael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin. vlsi 2013: 27-32 [doi]

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels BinarizedMichael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini. vlsi 2015: 144-167 [doi]

2012

High-speed compressed sensing reconstruction on FPGA using OMP and AMPLin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin. icecsys 2012: 53-56 [doi]

Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video ApplicationsPierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross. tcsv, 22(11):1577-1589, 2012. [doi]

Compressive sensing for WiFi-based passive bistatic radarPatrick Maechler, Norbert Felber, Hubert Kaeslin. eusipco 2012: 1444-1448 [doi]

Hardware-efficient random sampling of fourier-sparse signalsPatrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg. iscas 2012: 269-272 [doi]

Sparsity-based real-time audio restorationPatrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer. dasip 2012: 1-2 [doi]

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive SensingPatrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk. esticas, 2(3):579-590, 2012. [doi]

2008

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency MultipliersFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. tvlsi, 16(7):830-836, 2008. [doi]

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparisonPeter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. apccas 2008: 830-833 [doi]

2007

2006

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithmFelix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. dac 2006: 558-561 [doi]

42 power savings through glitch-reducing clocking strategy in a hearing aid applicationFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. iscas 2006: [doi]

Two-phase resonant clocking for ultra-low-power hearing aid applicationsFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. date 2006: 73-78 [doi]

GALS at ETH Zurich: Success or FailureFrank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. async 2006: 150-159 [doi]

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASICFrank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. ENTCS, 146(2):133-149, 2006. [doi]

2005

2004

A 2 Gb/s balanced AES crypto-chip implementationFrank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin. glvlsi 2004: 39-44 [doi]

Towards an AES crypto-chip resistant to differential power analysisNorbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. esscirc 2004: 307-310 [doi]

2003

2002

2001

Design and Verification of a Stack Processor Virtual ComponentManfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. micro, 21(2):69-80, 2001. [doi]

2000

A new paradigm for very flexible SONET/SDH IP-modulesThomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. cicc 2000: 533-536 [doi]

1999

Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processorManfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann. itc 1999: 414-420

1997

The impact of transistor sizing on power efficiency in submicron CMOS circuitsRobert Rogenmoser, Hubert Kaeslin. jssc, 32(7):1142-1145, 1997. [doi]

1996

Stochastic Methods for Transistor Size Optimization of CMOS VLSI CircuitsRobert Rogenmoser, Hubert Kaeslin, Tobias Blickle. ppsn 1996: 849-858

1994

A 177 Mb/s VLSI implementation of the International Data Encryption AlgorithmReto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. jssc, 29(3):303-307, March 1994. [doi]

1993

VINCI: Secure Test of a VLSI High-Speed Encryption SystemH. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner. itc 1993: 782-790

1991

VLSI Implementation of a New Block CipherH. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai. iccd 1991: 510-513

1989

Architectural design and realization of a single-chip Viterbi decoderMarc Biver, Hubert Kaeslin, Carlo Tommasini. integration, 8(1):3-16, 1989. [doi]

1988

Application of Graph Theory to Topology Generation for Logic GatesHubert Kaeslin. criwg 1989: 304-316

Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIXHubert Kaeslin. it, 30(1):11-16, 1988. [doi]

1986

A comparative study of the steady-state zones of German phones using centroids in the LPC parameter spaceHubert Kaeslin. speech, 5(1):35-46, 1986. [doi]

A systematic approach to the extraction of diphone elements from natural speechHubert Kaeslin. tsp, 34(2):264-271, 1986. [doi]

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