2009
- Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. tcad, 28(3):461-465, 2009. [doi]
- Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek. Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. tcad, 28(4):554-567, 2009. [doi]
2008
- Ilya Issenin, Nikil Dutt. Using FORAY Models to Enable MPSoC Memory Optimizations. ijpp, 36(1):93-113, 2008. [doi]
- Aviral Shrivastava, Ilya Issenin, Nikil Dutt. A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. aspdac 2008: 328-333 [doi]
- Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko. Compiler driven data layout optimization for regular/irregular array access patterns. lctrts 2008: 41-50 [doi]
- Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt. Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. tcad, 27(8):1439-1452, 2008. [doi]
2007
- Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek. Software controlled memory layout reorganization for irregular array access patterns. cases 2007: 179-188 [doi]
- Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt. DRDU: A data reuse analysis technique for efficient scratch-pad memory management. todaes, 12(2), 2007. [doi]
- Ilya Issenin, Nikil Dutt. Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. wiess 2007: 299-312 [doi]
2006
2005
2004
2002