Jürgen Teich - researchr alias

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2011

Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice VersaAndreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich. arcs 2011: 259-270 [doi]

Automatic generation of system-level virtual prototypes from streaming application modelsPhilipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich. rsp 2011: 128-134 [doi]

Opt4J: a modular framework for meta-heuristic optimizationMartin Lukasiewycz, Michael Glaß, Felix Reimann, Jürgen Teich. gecco 2011: 1723-1730 [doi]

Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image RegistrationRichard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert. arcs 2011: 62-73 [doi]

Dynamic decentralized mapping of tree-structured applications on NoC architecturesAndreas Weichslgartner, Stefan Wildermann, Jürgen Teich. nocs 2011: 201-208 [doi]

Self-organized Message Scheduling for Asynchronous Distributed Embedded SystemsTobias Ziermann, Zoran Salcic, Jürgen Teich. ATC 2011: 132-148 [doi]

2010

Model-based analysis, synthesis and testing of automotive hardware/software architecturesSamarjit Chakraborty, S. Ramesh, Jürgen Teich. emsoft 2010: 299-300 [doi]

21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski, editors, IEEE, 2010.

Analysis of SystemC actor networks for efficient synthesisJoachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya. tecs, 10(2):18, 2010. [doi]

A system-level synthesis approach from formal application models to generic bus-based MPSoCsJens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich. samos 2010: 118-125 [doi]

Towards scalable system-level reliability analysisMichael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich. dac 2010: 234-239 [doi]

Symbolic system level reliability analysisMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich. iccad 2010: 185-189 [doi]

Selected papers from the 18:::th::: International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]Udo Kebschull, Marco Platzner, Jürgen Teich. iet-cdt, 4(3):157-158, 2010. [doi]

Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded SystemsAndreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich. icccn 2010: 1-6 [doi]

Robust design of embedded systemsMartin Lukasiewycz, Michael Glaß, Jürgen Teich. date 2010: 1578-1583 [doi]

A rapid prototyping system for error-resilient multi-processor systems-on-chipMatthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich. date 2010: 375-380 [doi]

A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAsAndreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch. fpl 2010: 234-239 [doi]

Improving platform-based system synthesis by satisfiability modulo theories solvingFelix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich. codes 2010: 135-144 [doi]

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based SystemsJoon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich. fccm 2010: 179-182 [doi]

Self-organizing Computer Vision for Robust Object Tracking in Smart CamerasStefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic. ATC 2010: 1-16 [doi]

Efficient High-Level modeling in the networking domainChristian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch. date 2010: 1189-1194 [doi]

Using the Power Side Channel of FPGAs for CommunicationDaniel Ziener, Florian Baueregger, Jürgen Teich. fccm 2010: 237-244 [doi]

Multiplexing Methods for Power WatermarkingDaniel Ziener, Florian Baueregger, Jürgen Teich. host 2010: 36-41 [doi]

Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardwareTobias Ziermann, Jürgen Teich. ipps 2010: 1-4 [doi]

2009

General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systemsJosef Angermeier, Abdulazim Amouri, Jürgen Teich. fpl 2009: 302-307 [doi]

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance AnalysisHritam Dutta, Frank Hannig, Jürgen Teich. arcs 2009: 233-245 [doi]

Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop PartitioningFrank Hannig, Hritam Dutta, Jürgen Teich. arcs 2009: 16-27 [doi]

SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applicationsJoachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith. todaes, 14(1), 2009. [doi]

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable ArchitecturesDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich. jolpe, 5(1):96-105, 2009. [doi]

Hardware Decompression Techniques for FPGA-Based Embedded SystemsDirk Koch, Christian Beckhoff, Jürgen Teich. trets, 2(2), 2009. [doi]

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAsDirk Koch, Christian Beckhoff, Jürgen Teich. fpga 2009: 253-256 [doi]

Efficient approximately-timed performance modeling for architectural exploration of MPSoCsMartin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich. fdl 2009: 1-6 [doi]

Self-organizing multi-cue fusion for FPGA-based embedded imagingStefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich. fpl 2009: 132-137 [doi]

2008

Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheadsJosef Angermeier, Jürgen Teich. ipps 2008: 1-8 [doi]

Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance SystemJosef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele. arc 2008: 148-158 [doi]

Fine grain reconfigurable architecturesJosef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker. fpl 2008: 348 [doi]

Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant NetworksRobert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich. arcs 2008: 117-129 [doi]

A comparison of embedded reconfigurable video-processing architecturesChristopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich. fpl 2008: 587-590 [doi]

Coarse-grained reconfigurationSven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. fpl 2008: 349 [doi]

A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applicationsJoachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya. emsoft 2008: 189-198 [doi]

No-break dynamic defragmentation of reconfigurable devicesSándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich. fpl 2008: 113-118 [doi]

Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable DeviceSándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich. tvlsi, 16(9):1210-1219, 2008. [doi]

Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC ModelsJens Gladigau, Christian Haubelt, Jürgen Teich. fdl 2008: 1-6 [doi]

Multi-objective routing and topology optimization in networked embedded systemsMichael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich. samos 2008: 74-81 [doi]

Symbolic Reliability Analysis and Optimization of ECU NetworksMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich. date 2008: 158-163 [doi]

Symbolic Reliability Analysis of Self-healing Networked Embedded SystemsMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich. safecomp 2008: 139-152 [doi]

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive ApplicationsFrank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich. arc 2008: 284-289 [doi]

Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order CommunicationJoachim Keinert, Christian Haubelt, Jürgen Teich. arcs 2008: 130-143 [doi]

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable ArchitecturesDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich. patmos 2009: 307-317 [doi]

Efficient Reconfigurable On-Chip Buses for FPGAsDirk Koch, Christian Haubelt, Jürgen Teich. fccm 2008: 287-290 [doi]

ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGASDirk Koch, Christian Beckhoff, Jürgen Teich. fpl 2008: 119-124 [doi]

A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial ProblemsMartin Lukasiewycz, Michael Glaß, Jürgen Teich. ppsn 2008: 919-928 [doi]

A feasibility-preserving local search operator for constrained discrete optimization problemsMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. cec 2008: 1968-1975 [doi]

Concurrent topology and routing optimization in automotive network integrationMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang. dac 2008: 626-629 [doi]

Efficient symbolic multi-objective design space explorationMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. aspdac 2008: 691-696 [doi]

Symbolic voter placement for dependability-aware system synthesisFelix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich. codes 2008: 237-242 [doi]

Topology-Aware Replica Placement in Fault-Tolerant Embedded NetworksThilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich. arcs 2008: 23-37 [doi]

Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen)Jürgen Teich. it, 50(5):300-310, 2008.

3D Person Tracking with a Color-Based Particle FilterStefan Wildermann, Jürgen Teich. robvis 2008: 327-340 [doi]

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array ArchitecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. fccm 2008: 306-309 [doi]

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. fpl 2008: 391-396 [doi]

Classification of General Data Flow Actors into Known Models of ComputationChristian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich. memocode 2008: 119-128 [doi]

Power Signature Watermarking of IP Cores for FPGAsDaniel Ziener, Jürgen Teich. vlsisp, 51(1):123-136, 2008. [doi]

Concepts for Autonomous Control Flow Checking for Embedded CPUsDaniel Ziener, Jürgen Teich. ATC 2008: 234-248 [doi]

2007

The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen. it, 49(3):143, 2007. [doi]

Dynamically Reconfigurable ArchitecturesNeil Bergmann, Marco Platzner, Jürgen Teich. ejes, 2007, 2007. [doi]

Efficient control generation for mapping nested loop programs onto processor arraysHritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich. jsa, 53(5-6):300-309, 2007. [doi]

Massively Parallel Processor Architectures: A Co-design ApproachHritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier. recosoc 2007: 61-68

Mapping Actor-Oriented Models to TLM ArchitecturesJens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich. fdl 2007: 128-133 [doi]

Interactive presentation: Reliability-aware system synthesisMichael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich. date 2007: 409-414 [doi]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich, editors, ACM, 2007.

A SystemC-Based Design Methodology for Digital Signal Processing SystemsChristian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich. ejes, 2007, 2007. [doi]

Actor-Oriented Modeling and Simulation of Sliding Window Image Processing AlgorithmsJoachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich. estimedia 2007: 113-118 [doi]

Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data FlowJoachim Keinert, Christian Haubelt, Jürgen Teich. samos 2007: 161-168 [doi]

Modeling and Synthesis of Hardware-Software MorphingDirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich. iscas 2007: 2746-2749 [doi]

Efficient hardware checkpointing: concepts, overhead analysis, and implementationDirk Koch, Christian Haubelt, Jürgen Teich. fpga 2007: 188-196 [doi]

Efficient event-driven simulation of parallel processor architecturesAlexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich. scopes 2007: 71-80 [doi]

Modeling of Interconnection Networks in Massively Parallel Processor ArchitecturesAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement. arcs 2007: 268-282 [doi]

Solving Multi-objective Pseudo-Boolean ProblemsMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. sat 2007: 56-69 [doi]

SAT-decoding in evolutionary algorithms for discrete constrained optimization problemsMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. cec 2007: 935-942 [doi]

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based ComputerMateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda. vlsisp, 47(1):15-31, 2007. [doi]

Design space exploration of reliable networked embedded systemsThilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich. jsa, 53(10):751-763, 2007. [doi]

Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme)Jürgen Teich. it, 49(3):139, 2007. [doi]

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative EvaluationJürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet. ersa 2007: 14-24

2006

Hierarchical Partitioning for Piecewise Linear AlgorithmsHritam Dutta, Frank Hannig, Jürgen Teich. parelec 2006: 153-160 [doi]

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image ProcessingHritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger. asap 2006: 331-340 [doi]

Efficient Representation and Simulation of Model-Based DesignsJoachim Falk, Christian Haubelt, Jürgen Teich. fdl 2006: 129-135 [doi]

Minimizing Communication Cost for Reconfigurable Slot ModulesSándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich. fpl 2006: 1-6 [doi]

Higher-Dimensional Packing with Order ConstraintsSándor P. Fekete, Ekkehard Köhler, Jürgen Teich. siamdm, 20(4):1056-1078, 2006. [doi]

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot MachineDiana Göhringer, Mateusz Majer, Jürgen Teich. dagstuhl 2006: [doi]

A Generic Framework for Rapid Prototyping of System-on-Chip DesignsDmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich. cdes 2006: 189-195

Searching RC5-Keys with Distributed Reconfigurable ComputingDirk Koch, Matthiaas Koerber, Jürgen Teich. ersa 2006: 42-48

An Operating System Infrastructure for Fault-Tolerant Reconfigurable NetworksDirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich. arcs 2006: 202-216 [doi]

Symbolic Archive Representation for a Fast Nondominance TestMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. emo 2007: 111-125 [doi]

A Flexible Reconfiguration Manager for the Erlangen Slot MachineMateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich. arcs 2006: 183-194

Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary AlgorithmsThomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich. isvlsi 2006: 309-316 [doi]

Dynamic task binding for hardware/software reconfigurable networksThilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich. sbcci 2006: 38-43 [doi]

Multi-Objective Topology Optimization for Networked Embedded SystemsThilo Streichert, Christian Haubelt, Jürgen Teich. samos 2006: 93-98 [doi]

Topic 18: Embedded Parallel SystemsJürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner. europar 2006: 1179 [doi]

Are current ESL tools meeting the requirements of advanced embedded systems?Jürgen Teich. codes 2006: 166 [doi]

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