Jean-Luc Nagel - researchr alias

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Viewing Publication 1 - 19 from 19

2019

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mWJian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery. islped 2019: 1-4 [doi]

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDCChristoph Thomas Müller, Marc Pons, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi. prime 2019: 285-288 [doi]

A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOSMarc Pons, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi. cicc 2019: 1-4 [doi]

2016

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operationMarc Pons, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stephane Emery. esscirc 2016: 41-44 [doi]

2013

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operationMarc Pons, Jean-Luc Nagel, Daniel Séverac, Marc-Nicolas Morgan, Daniel Sigg, Pierre-François Ruedi, Christian Piguet. patmos 2013: 9-15 [doi]

2012

Maximum delay variation temperature-aware standard cell designMarc Pons, Jean-Luc Nagel, Christian Piguet. icecsys 2012: 296-299 [doi]

2011

Energy parsimonious circuit design through probabilistic pruningLingamneni Avinash, Christian C. Enz, Jean-Luc Nagel, Krishna V. Palem, Christian Piguet. date 2011: 764-769 [doi]

2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital CircuitsLuca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino. jolpe, 6(1):44-55, 2010. [doi]

2009

2008

Low-Power Heterogeneous Systems-on-ChipsChristian Piguet, Jean-Luc Nagel, Vincent Peiris, Steve Gyger, Daniel Séverac, Marc Morgan, Jean-Marc Masgonty. jolpe, 4(2):111-126, 2008. [doi]

2006

Static and Dynamic Power Reduction by Architecture SelectionChristian Piguet, Christian Schuster, Jean-Luc Nagel. patmos 2006: 659-668 [doi]

Architectural and technology influence on the optimal total power consumptionChristian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine. date 2006: 989-994 [doi]

2005

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and VthChristian Schuster, Christian Piguet, Jean-Luc Nagel, Pierre-André Farine. jolpe, 1(1):3-10, 2005. [doi]

2004

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier ArchitecturesChristian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine. patmos 2004: 169-178 [doi]

2003

Optimized filterbank fingerprint recognitionErian Bezhani, Dequn Sun, Jean-Luc Nagel, Sergio Carrato. ipas 2003: 399-406 [doi]

2002

A low-power VLSI architecture for face verification using elastic graph matchingJean-Luc Nagel, Patrick Stadelmann, Michael Ansorge, Fausto Pellandini. eusipco 2002: 1-4 [doi]

A multiscale morphological coprocessor for low-power face authenticationPatrick Stadelmann, Jean-Luc Nagel, Michael Ansorge, Fausto Pellandini. eusipco 2002: 1-4 [doi]

2000

A low-complexity video coder based on the Discrete Walsh Hadamard TransformRoberto Costantini, Javier Bracamonte, G. Ramponi, Jean-Luc Nagel, Michael Ansorge, Fausto Pellandini. eusipco 2000: 1-4 [doi]

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