Jian-Fei Jiang - researchr alias

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Viewing Publication 1 - 24 from 24

2022

A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection NetworkJian-Fei Jiang, Mingjun Jiang, Jiayu Zhang, Feng Dong. tcasII, 69(6):2947-2951, 2022. [doi]

2020

An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible ArchitectureJiaming Tu, Mengdan Lou, Jian-Fei Jiang, Dewu Shu, Guanghui He. tcas, 67-I(11):4015-4028, 2020. [doi]

Priority Branches for Ship Detection in Optical Remote Sensing ImagesYijia Zhang, Weiguang Sheng, Jian-Fei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao. remotesensing, 12(7):1196, 2020. [doi]

2019

2017

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiencyXuwei Jin, Wei Jin, Hao Zhang, Jian-Fei Jiang, Weifeng He. iscas 2017: 1-4 [doi]

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOSWei Jin, Weifeng He, Jian-Fei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing. integration, 58:27-34, 2017. [doi]

A metastability-based true random number generator on FPGAChaoyang Li, Qin Wang, Jian-Fei Jiang, Nin Guan. asicon 2017: 738-741 [doi]

An on-chip circuit for timing measurement of SRAM IPXianjie Long, Qin Wang, Jian-Fei Jiang, Nin Guan. asicon 2017: 569-572 [doi]

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D ICQin Wang, Zhenyang Chen, Jian-Fei Jiang, Zheng Guo, Zhigang Mao. integration, 59:23-30, 2017. [doi]

2016

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global InterconnectsJian-Fei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He. jcsc, 25(10):1-31, 2016. [doi]

Parallel SER analysis for combinational and sequential standard cell circuitsWeiguang Sheng, Jian-Fei Jiang, Zhigang Mao. mj, 50:8-19, 2016. [doi]

2015

A crosstalk avoidance scheme based on re-layout of signal TSVJiayi Hu, Qin Wang, Jian-Fei Jiang, Jing Xie, Zhigang Mao. asicon 2015: 1-4 [doi]

Design optimization for capacitive-resistively driven on-chip global interconnectJian-Fei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao. ieiceee, 12(8):20150111, 2015. [doi]

A contactless testing methodology for pre-bond interposerJian-Fei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao. mwscas 2015: 1-4 [doi]

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAsNaifeng Jing, Jiacheng Zhou, Jian-Fei Jiang, Xin Chen, Weifeng He, Zhigang Mao. iccad 2015: 764-769 [doi]

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel PreprocessingZhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jian-Fei Jiang, Zhigang Mao. tcas, 62-I(11):2706-2717, 2015. [doi]

2012

A pre-emphasis circuit design for high speed on-chip global interconnectJian-Fei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He. iscas 2012: 2941-2944 [doi]

2011

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