Jiann-Chyi Rau - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 25 from 25

2021

A Scan-Based Lower-Power Testing Architecture for Modern CircuitsJiann-Chyi Rau, Jia-Xiang Wang. ispacs 2021: 1-2 [doi]

2013

Compact Test Pattern Selection for Small Delay DefectChia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau. tcad, 32(6):971-975, 2013. [doi]

2012

Optimal unknown bit filtering for test response maskingDing-ke Weng, Jiann-Chyi Rau, Cheng-Han Lin. ispacs 2012: 787-791 [doi]

2011

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environmentJiann-Chyi Rau, Po-Han Wu. iet-cdt, 5(1):25-35, 2011. [doi]

2010

2009

New Scheme of Reducing Shift and Capture Power Using the X-Filling MethodologyTsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau. ats 2009: 105-110 [doi]

Reducing Switching Activity by Test Slice Difference Technique for Test Volume CompressionWei-Lin Li, Po-Han Wu, Jiann-Chyi Rau. iscas 2009: 2986-2989 [doi]

Low power multi-chains encoding scheme for SoC in low-cost environmentPo-Han Wu, Jiann-Chyi Rau. itc 2009: 1 [doi]

2008

2006

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCsJiann-Chyi Rau, Chien-Shiun Chen, Po-Han Wu. apccas 2006: 1399-1402 [doi]

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI CircuitsJiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu. apccas 2006: 1883-1886 [doi]

A broadcast-based test scheme for reducing test size and application timeJiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen. iscas 2006: [doi]

2005

A novel reseeding mechanism for pseudo-random testing of VLSI circuitsJiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu. iscas 2005: 2979-2982 [doi]

Reconfigurable multiple scan-chains for reducing test application time of SOCsJiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma. iscas 2005: 5846-5849 [doi]

2004

An Efficient Low-Overhead Policy for Constructing Multiple Scan-ChainsJiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang. ats 2004: 82-87 [doi]

2003

An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI CircuitsJiann-Chyi Rau, Kuo-Chun Kuo. iwsoc 2003: 374-377 [doi]

An Efficient Mechanism for Debugging RTL DescriptionJiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin. iwsoc 2003: 370-373 [doi]

2002

A don t-care based image circuit for function verificationJiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang. iscas 2002: 325-328 [doi]

2001

A timing-driven pseudoexhaustive testing for VLSI circuitsShih-Chieh Chang, Jiann-Chyi Rau. tcad, 20(1):147-158, 2001. [doi]

2000

A compact factored form for a Boolean functionJiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang. iscas 2000: 317-320 [doi]

1998

A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuitsWen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu. itc 1998: 322-330 [doi]

Sign in or sign up to see more results.

runs on WebDSL