Jiren Yuan - researchr alias

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2007

A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOSCheng Chen, Jiren Yuan. iscas 2007: 1709-1712 [doi]

2005

Design considerations of a floating-point ADC with embedded S/HJohan Piper, Jiren Yuan. iscas 2005: 6166-6169 [doi]

2004

A CMOS 500 MS/S charge samplerGang Xu, Jiren Yuan. iastedCCS 2004: 462-466

A programmable analog-to-digital converterGang Xu, Jiren Yuan. iscas 2004: 585-588 [doi]

2003

A Differential Difference Comparator for multi-step A/D convertersGang Xu, Jiren Yuan. iscas 2003: 257-260 [doi]

Performance analysis of general charge samplingGang Xu, Jiren Yuan. iscas 2003: 745-748 [doi]

An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error averageLixin Yang, Jiren Yuan. iscas 2003: 645-648 [doi]

2002

A non-feedback multiphase clock generatorLixin Yang, Yijun Zhou, Jiren Yuan. iscas 2002: 389-392 [doi]

A direct digital RF amplitude modulatorYijun Zhou, Jiren Yuan. iscas 2002: 141-144 [doi]

2001

Realization of a floating-point A/D converterJohan Piper, Jiren Yuan. iscas 2001: 404-407 [doi]

An embedded low power FIR filterGang Xu, Jiren Yuan. iscas 2001: 230-233 [doi]

An 8-Bit, 100-MHz low glitch interpolation DACYijun Zhou, Jiren Yuan. iscas 2001: 116-119 [doi]

1993