João Paulo Teixeira - researchr alias

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2011

2010

2009

Data Acquisition Electronics for PET Mammography ImagingCarlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, Joel Rego, Pedro Neves, Fernando Piedade, Pedro Lousã, Pedro Rodrigues, Andreia Trindade, R. Bugalho, J. F. Pinheiro, M. Ferreira, João Varela. biostec 2009: 192-197

2008

2007

Functional-oriented mask-based built-in self-testMarcelino B. Santos, João Paulo Teixeira. iet-cdt, 1(5):491-498, 2007. [doi]

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature VariationsJorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira. dft 2007: 303-311 [doi]

Enhancing the Tolerance to Power-Supply Instability in Digital CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. isvlsi 2007: 207-212 [doi]

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. iolts 2007: 167-172 [doi]

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. ddecs 2007: 295-300

2006

Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults CoverageF. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. ddecs 2006: 279-284

Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature SchemesMarcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira. iolts 2006: 257-262 [doi]

2005

2004

2003

On the Use of Prosodic Labelling in Corpus-Based Linguistic Studies of Spontaneous SpeechDaniela Braga, Diamantino Freitas, João Paulo Teixeira, Aldina Marques. TSD 2003: 388-393 [doi]

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe SystemsFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. iolts 2003: 164-165 [doi]

Fault Simulation Using Partially Reconfigurable HardwareA. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa. fpl 2003: 839-848 [doi]

RTL Test Pattern Generation for High Quality Loosely Deterministic BISTMarcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira. date 2003: 10994-10999 [doi]

Prediction of fujisaki model s phrase commandsJoão Paulo Teixeira, Diamantino Freitas, Hiroya Fujisaki. interspeech 2003: [doi]

Evaluation of a Segmental Durations Model for TTSJoão Paulo Teixeira, Diamantino Freitas. propor 2003: 40-48 [doi]

2002

A Project of Speech Input and Output in an E-commerce ApplicationDiamantino Freitas, António Moura, Daniela Braga, Helder Ferreira, João Paulo Teixeira, Maria João Barros, Paulo Gouveia, Vagner Latsch. portal 2002: 141-150 [doi]

Self-Checking and Fault Tolerance Quality Assessment Using Fault SamplingFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. dft 2002: 216-224 [doi]

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control SystemFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. et, 18(3):285-294, 2002. [doi]

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BISTMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras. itc 2002: 814-823 [doi]

RTL Design Validation, DFT and Test Pattern Generation for High Defects CoverageMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. et, 18(2):179-187, 2002. [doi]

2001

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-levelFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. itc 2001: 377-385

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners ControFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. iolts 2001: 197-201 [doi]

Towards E-Management as Enabler for Accelerated ChangeHugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira. ICEIS 2001: 807-814

RTL-Based Functional Test Generation for High Defects Coverage in Digital SystemsMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. et, 17(3-4):311-319, 2001. [doi]

Phonetic events from the labeling the european portuguese database for speech synthesis, FEUP/IPBDBJoão Paulo Teixeira, Diamantino Freitas, Daniela Braga, Maria João Barros, Vagner Latsch. interspeech 2001: 1707-1710 [doi]

Embedded tutorial: TRP: integrating embedded test and ATEYervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher. date 2001: 34-37 [doi]

2000

1999

Developing a voiced information retrieval system for the portuguese language capable to handle both brazilian and portuguese spoken versionsMárcio N. de Souza, E. J. Caprini, Glaucio J. Couri Machado, M. V. Ludolf, Luiz Pereira Calôba, José Manoel de Seixas, Fernando Gil Resende, Sergio L. Netto, Diamantino Rui da Silva Freitas, João Paulo Teixeira, Carlos Espain, Vitor Pera, F. Moreira. interspeech 1999: [doi]

Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems ArchitecturesOctávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira. et, 14(1-2):149-158, 1999. [doi]

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI SystemsFernando M. Gonçalves, João Paulo Teixeira. et, 15(1-2):41-52, 1999. [doi]

Teaching Microelectronic-Based Integrated Systems Design and TestFernando M. Gonçalves, João Paulo Teixeira. mse 1999: 65-66 [doi]

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDLMarcelino B. Santos, João Paulo Teixeira. date 1999: 549 [doi]

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling TechniqueMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. vts 1999: 326-332 [doi]

1998

An OO Based Methodology for Real-Time HW/SW Systems ModelingOctávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira. ifip10-3 1999: 213-222

Sampling Techniques of Non-Equally Probable Faults in VLSI SystemFernando M. Gonçalves, João Paulo Teixeira. vts 1998: 283-288 [doi]

Defect-oriented test quality assessment using fault sampling and simulationFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. itc 1998: 35-42 [doi]

1997

Realistic Fault Extraction for High-Quality Design and Test of VLSI SystemsFernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. dft 1997: 29-37 [doi]

1996

Defect-Oriented IC Test and Diagnosis Using VHDL Fault SimulationF. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira. itc 1996: 620-628

Defect level evaluation in an IC design environmentJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams. tcad, 15(10):1286-1293, 1996. [doi]

1995

Test preparation for high coverage of physical defects in CMOS digital ICsMarcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira. vts 1995: 330-337 [doi]

1994

Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICsM. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. itc 1994: 720-728

On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital CircuitsAntonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos. dft 1994: 263-270

Fault Modeling and Defect Level Projections in Digital ICsJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams. eurodac 1994: 436-442

1993

Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS DesignsAntonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. dft 1993: 109-116

Realistic Fault Analysis of CMOS Analog Building BlocksP. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. dft 1993: 311-318

1992

Physical DFT for High Coverage of Realistic FaultsM. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. itc 1992: 642-651

1991

IC Defects-Based Testability AnalysisJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira. itc 1991: 500-509

A methodology for testability enhancement at layout levelJoão Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves. et, 1(4):287-299, 1991. [doi]

1990

A strategy for testability enhancement at layout levelJoão Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo. eurodac 1990: 413-417 [doi]