José T. de Sousa - researchr alias

researchr

You are not signed in
Sign in
Sign up

2008

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtractionRomanelli Lodron Zuim, José T. de Sousa, Claudionor N. Coelho. iet-cdt, 2(1):30-39, 2008. [doi]

2006

A fast SAT solver algorithm best suited to reconfigurable hardwareRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. sbcci 2006: 131-136 [doi]

A Fast SAT Solver Strategy Based on Negated ClausesRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. vlsi 2006: 110-115 [doi]

2005

Heuristic-Based Backtracking Relaxation for Propositional SatisfiabilityAteet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva. JAR, 35(1-3):3-24, 2005. [doi]

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital CircuitsVictor Gonçalves, José T. de Sousa, Fernando M. Gonçalves. fpl 2005: 481-486

2004

Guest Editors Introduction: Field Programmable Logic and ApplicationsPeter Y. K. Cheung, George A. Constantinides, José T. de Sousa. TC, 53(11):1361-1362, 2004. [doi]

Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded ProcessorC. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa. fpl 2004: 344-353 [doi]

2003

2002

DARP - A Digital Audio Reconfigurable ProcessorJosé T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura. fpl 2002: 556-566 [doi]

On Implementing a Configware/Software SAT SolverN. A. Reis, José T. de Sousa. fccm 2002: 282-283 [doi]

2000

A SAT Solver Using Reconfigurable Hardware and Virtual LogicMiron Abramovici, José T. de Sousa. JAR, 24(1/2):5-36, 2000.

Reducing the Complexity of Defect Level Modeling Using the Clustering EffectJosé T. de Sousa, Vishwani D. Agrawal. date 2000: 640-644 [doi]

1999

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa, Daniel G. Saab. dac 1999: 684-690 [doi]

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa. fccm 1999: 306-307 [doi]

On Defect-Level Estimation and the Clustering EffectJosé T. de Sousa. ifip10-5 2000: 257-268

1997

Improved diagnosis of realistic interconnect shortsJosé T. de Sousa, Peter Y. K. Cheung. date 1997: 501-505 [doi]

Diagnosis of Boards for Realistic Interconnect ShortsJosé T. de Sousa, Peter Y. K. Cheung. et, 11(2):157-171, 1997. [doi]

1996

Defect level evaluation in an IC design environmentJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams. tcad, 15(10):1286-1293, 1996. [doi]

1994

Fault Modeling and Defect Level Projections in Digital ICsJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams. eurodac 1994: 436-442

1992

Physical DFT for High Coverage of Realistic FaultsM. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. itc 1992: 642-651

1991

IC Defects-Based Testability AnalysisJosé T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira. itc 1991: 500-509