Josep Torrellas - researchr alias

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2011

Rebound: scalable checkpointing for coherent shared memoryRishi Agarwal, Pranav Garg, Josep Torrellas. isca 2011: 153-164 [doi]

FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashesRishi Agarwal, Josep Torrellas. isca 2011: 33-44 [doi]

2010

LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicoresBrian Greskamp, Ulya R. Karpuzcu, Josep Torrellas. hpca 2010: 1-12 [doi]

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation DetectionAbdullah Muzahid, Norimasa Otsuki, Josep Torrellas. micro 2010: 287-297 [doi]

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental HashingAdrian Nistor, Darko Marinov, Josep Torrellas. micro 2010: 251-262 [doi]

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy EnvironmentXuehai Qian, Wonsun Ahn, Josep Torrellas. micro 2010: 447-458 [doi]

Extreme scale computing: Challenges and opportunitiesJosep Torrellas, Bill Gropp, Vivek Sarkar, Jaime Moreno, Kunle Olukotun. hpca 2010: 1 [doi]

Extreme scale computing: challenges and opportunitiesJosep Torrellas, Bill Gropp, Jaime Moreno, Kunle Olukotun, Vivek Sarkar. ppopp 2010: 101-102 [doi]

2009

BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware supportWonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J. W. Lee, Xing Fang, Samuel P. Midkiff, David Wong. micro 2009: 133-144 [doi]

Blueshift: Designing processors for timing speculation from the ground upBrian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles. hpca 2009: 213-224 [doi]

Two hardware-based approaches for deterministic multiprocessor replayDerek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas. CACM, 52(6):93-100, 2009. [doi]

The BubbleWrap many-core: popping cores for sequential accelerationUlya R. Karpuzcu, Brian Greskamp, Josep Torrellas. micro 2009: 447-458 [doi]

Capo: a software-hardware interface for practical deterministic multiprocessor replayPablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas. asplos 2009: 73-84 [doi]

SigRace: signature-based data race detectionAbdullah Muzahid, Dario Suárez, Shanxiang Qi, Josep Torrellas. isca 2009: 337-348 [doi]

Light64: lightweight hardware support for data race detection during systematic testing of parallel programsAdrian Nistor, Darko Marinov, Josep Torrellas. micro 2009: 541-552 [doi]

How to build a useful thousand-core manycore system?Josep Torrellas. ipps 2009: 1 [doi]

Architectures for Extreme-Scale ComputingJosep Torrellas. Computer, 42(11):28-35, 2009. [doi]

The Bulk Multicore architecture for improved programmabilityJosep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, Milos Prvulovic. CACM, 52(12):58-65, 2009. [doi]

SoftSig: Software-Exposed Hardware Signatures for Code Analysis and OptimizationJames Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze. micro, 29(1):84-95, 2009. [doi]

2008

Concurrency control with data coloringLuis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, Josep Torrellas. asplos 2008: 6-10 [doi]

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution EffcientlyPablo Montesinos, Luis Ceze, Josep Torrellas. isca 2008: 289-300 [doi]

EVAL: Utilizing processors with variation-induced timing errorsSmruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas. euromicro 2008: 423-434 [doi]

Variation-Aware Application Scheduling and Power Management for Chip MultiprocessorsRadu Teodorescu, Josep Torrellas. isca 2008: 363-374 [doi]

Facelift: Hiding and slowing down aging in multicoresAbhishek Tiwari, Josep Torrellas. euromicro 2008: 129-140 [doi]

SoftSig: software-exposed hardware signatures for code analysis and optimizationJames Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas. asplos 2008: 145-156 [doi]

2007

Estimating design time for system circuitsCyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau. vlsi 2007: 60-65 [doi]

BulkSC: bulk enforcement of sequential consistencyLuis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas. isca 2007: 278-289 [doi]

Colorama: Architectural Support for Data-Centric SynchronizationLuis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas. hpca 2007: 133-144 [doi]

Threshold Voltage Variation Effects on Aging-Related Hard Failure RatesBrian Greskamp, Smruti R. Sarangi, Josep Torrellas. iscas 2007: 1261-1264 [doi]

Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core OverclockingBrian Greskamp, Josep Torrellas. IEEEpact 2007: 213-224 [doi]

Using Register Lifetime Predictions to Protect Register Files against Soft ErrorsPablo Montesinos, Wei Liu, Josep Torrellas. dsn 2007: 286-296 [doi]

Patching Processor Design Errors with Programmable HardwareSmruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas. micro, 27(1):12-25, 2007. [doi]

A Model for Timing Errors in Processors with Parameter VariationSmruti R. Sarangi, Brian Greskamp, Josep Torrellas. isqed 2007: 647-654 [doi]

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring MultiprocessorsKarin Strauss, Xiaowei Shen, Josep Torrellas. micro 2007: 327-342 [doi]

Mitigating Parameter Variation with Dynamic Fine-Grain Body BiasingRadu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas. micro 2007: 27-42 [doi]

ReCycle: : pipeline adaptation to tolerate process variationAbhishek Tiwari, Smruti R. Sarangi, Josep Torrellas. isca 2007: 323-334 [doi]

CAP: Criticality analysis for power-efficient speculative multithreadingJames Tuck, Wei Liu, Josep Torrellas. iccd 2007: 409-416 [doi]

2006

CAVA: Using checkpoint-assisted value prediction to hide L2 missesLuis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau. taco, 3(2):182-208, 2006. [doi]

Bulk Disambiguation of Speculative Threads in MultiprocessorsLuis Ceze, James Tuck, Josep Torrellas, Calin Cascaval. isca 2006: 227-238 [doi]

POSH: a TLS compiler that exploits program structureWei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas. ppopp 2006: 158-167 [doi]

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug DetectionShan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas. micro 2006: 38-52 [doi]

ReViveI/O: efficient handling of I/O in highly-available rollback-recovery serversJun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas. hpca 2006: 200-211 [doi]

Energy-Efficient Thread-Level SpeculationJose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas. micro, 26(1):80-91, 2006. [doi]

Accurate and efficient filtering for the Intel thread checker race detectorPaul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas. asplos 2006: 34-41 [doi]

CADRE: Cycle-Accurate Deterministic Replay for Hardware DebuggingSmruti R. Sarangi, Brian Greskamp, Josep Torrellas. dsn 2006: 301-312 [doi]

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable HardwareSmruti R. Sarangi, Abhishek Tiwari, Josep Torrellas. micro 2006: 26-37 [doi]

Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring MultiprocessorsKarin Strauss, Xiaowei Shen, Josep Torrellas. isca 2006: 327-338 [doi]

SWICH: A Prototype for Efficient Cache-Level Checkpointing and RollbackRadu Teodorescu, Jun Nakano, Josep Torrellas. micro, 26(5):28-40, 2006. [doi]

Guest Editor s Introduction: Micro s Top Picks from Microarchitecture ConferencesJosep Torrellas. micro, 26(1):8-9, 2006. [doi]

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006Josep Torrellas, Siddhartha Chatterjee, editors, ACM, 2006.

Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006Josep Torrellas, editor, ACM, 2006.

Scalable Cache Miss Handling for High Memory-Level ParallelismJames Tuck, Luis Ceze, Josep Torrellas. micro 2006: 409-422 [doi]

2005

Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessorsMaría Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas. taco, 2(3):247-279, 2005. [doi]

Thread-Level Speculation on a CMP can be energy efficientJose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas. ics 2005: 219-228 [doi]

Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilationJose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas. ics 2005: 179-188 [doi]

Prototyping Architectural Support for Program Rollback Using FPGAsRadu Teodorescu, Josep Torrellas. fccm 2005: 23-32 [doi]

Efficient and flexible architectural support for dynamic monitoringYuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas. taco, 2(1):3-33, 2005. [doi]

2004

2003

Programming the FlexRAM parallel intelligent memory systemBasilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas. ppopp 2003: 49-60 [doi]

Tradeoffs in Buffering Memory State for Thread-Level Speculation in MultiprocessorsMaría Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas. hpca 2003: 191-202 [doi]

Using Software Logging to Support Multi-Version Buffering in Thread-Level SpeculationMaría Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas. IEEEpact 2003: 170 [doi]

Positional Adaptation of Processors: Application to Energy ReductionMichael C. Huang, Jose Renau, Josep Torrellas. isca 2003: 157-168 [doi]

Speculative Synchronization: Programmability and Performance for Parallel CodesJosé F. Martínez, Josep Torrellas. micro, 23(6):126-134, 2003. [doi]

Design Trade-Offs in High-Throughput Coherence ControllersAnthony-Trung Nguyen, Josep Torrellas. IEEEpact 2003: 194-205 [doi]

ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded CodesMilos Prvulovic, Josep Torrellas. isca 2003: 110-121

Correlation Prefetching with a User-Level Memory ThreadYan Solihin, Jaejin Lee, Josep Torrellas. tpds, 14(6):563-580, 2003. [doi]

2002

Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for MultiprocessorsMarcelo H. Cintra, Josep Torrellas. hpca 2002: 43-54 [doi]

SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction OperationsFrancis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas. ipps 2002: [doi]

Energy-efficient hybrid wakeup logicMichael C. Huang, Jose Renau, Josep Torrellas. islped 2002: 196-201 [doi]

Speculative synchronization: applying thread-level speculation to explicitly parallel applicationsJosé F. Martínez, Josep Torrellas. asplos 2002: 18-29 [doi]

Cherry: checkpointed early resource recycling in out-of-order microprocessorsJosé F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas. euromicro 2002: 3-14 [doi]

ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory MultiprocessorsMilos Prvulovic, Josep Torrellas, Zheng Zhang. isca 2002: 111-122 [doi]

Software Trace Cache for Commercial ApplicationsAlex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas. ijpp, 30(5):373-395, 2002.

Using a User-Level Memory Thread for Correlation PrefetchingYan Solihin, Josep Torrellas, Jaejin Lee. isca 2002: 171-182 [doi]

2001

Architectural Support for Parallel Reductions in Scalable Shared-Memory MultiprocessorsMaría Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger. IEEEpact 2001: 243 [doi]

L1 data cache decomposition for energy efficiencyMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. islped 2001: 10-15 [doi]

The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature ManagementMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. jilp, 3, 2001. [doi]

The Need for Fast Communication in Hardware-Based Speculative Chip MultiprocessorsVenkata Krishnan, Josep Torrellas. ijpp, 29(1):3-33, 2001.

Automatically Mapping Code on an Intelligent Memory ArchitectureJaejin Lee, Yan Solihin, Josep Torrellas. hpca 2001: 121 [doi]

Removing architectural bottlenecks to the scalability of speculative parallelizationMilos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas. isca 2001: 204-215 [doi]

Automatic Code Mapping on an Intelligent Memory ArchitectureYan Solihin, Jaejin Lee, Josep Torrellas. TC, 50(11):1248-1266, 2001. [doi]

2000

Unified Fine-Granularity Buffering of Index and Data: Approach and ImplementationQiang Cao, Josep Torrellas, H. V. Jagadish. iccd 2000: 175-186 [doi]

Architectural support for scalable speculative parallelization in shared-memory multiprocessorsMarcelo H. Cintra, José F. Martínez, Josep Torrellas. isca 2000: 13-24 [doi]

A framework for dynamic energy efficiency and temperature managementMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. euromicro 2000: 202-213 [doi]

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory ChipsMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. ims 2001: 152-159 [doi]

SmartApps: An Application Centric Approach to High Performance ComputingLawrence Rauchwerger, Nancy M. Amato, Josep Torrellas. lcpc 2001: 82-96 [doi]

Adaptively Mapping Code in an Intelligent Memory ArchitectureYan Solihin, Jaejin Lee, Josep Torrellas. ims 2001: 71-84 [doi]

Toward a Cost-Effective DSM Organization That Exploits Processor-Memory IntegrationJosep Torrellas, Liuxi Yang, Anthony-Trung Nguyen. hpca 2000: 15-25 [doi]

1999

Detailed Characterization of a Quad Pentium Pro Server Running TPC-DQiang Cao, Josep Torrellas, Pedro Trancoso, Josep-Lluis Larriba-Pey, Bob Knighten, Youjip Won. iccd 1999: 108 [doi]

FlexRAM: Toward an Advanced Intelligent Memory SystemYi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik. iccd 1999: 192-201 [doi]

Compiler Support for Data Forwarding in Scalable Shared-Memory MultiprocessorsDavid Koufaty, Josep Torrellas. icpp 1999: 181 [doi]

Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivityJosé F. Martínez, Josep Torrellas, José Duato. ics 1999: 202-209 [doi]

Optimization of Instruction Fetch for Decision Support WorkloadsAlex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas. icpp 1999: 238-245 [doi]

Software trace cacheAlex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero. ics 1999: 119-126 [doi]

Cache Optimization for Memory-Resident Decision Support Commercial WorkloadsPedro Trancoso, Josep Torrellas. iccd 1999: 546 [doi]

Comprehensive Hardware and Software Support for Operating Systems to ExploitChun Xia, Josep Torrellas. TC, 48(5):494-505, 1999.

Excel-NUMA: Toward Programmability, Simplicity, and High PerformanceZheng Zhang, Marcelo H. Cintra, Josep Torrellas. TC, 48(2):256-264, 1999. [doi]

Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM MultiprocessorsYe Zhang, Lawrence Rauchwerger, Josep Torrellas. hpca 1999: 135 [doi]

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