Joshua Fazekas - researchr alias

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Viewing Publication 1 - 9 from 9

2007

An automated, FPGA-based reconfigurable, low-power RFID tagAlex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. mam, 31(2):116-134, 2007. [doi]

2006

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware FunctionsRaymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud. ejasp, 2006, 2006. [doi]

A Field Programmable RFID Tag and Associated Design FlowAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. fccm 2006: 165-174 [doi]

An automated, reconfigurable, low-power RFID tagAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. dac 2006: 131-136 [doi]

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing PowerAlex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas. tcas, 53-II(11):1250-1254, 2006. [doi]

Reducing power while increasing performance with superciscAlex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster. tecs, 5(3):658-686, 2006. [doi]

2005

An FPGA-based VLIW processor with custom hardware executionAlex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster. fpga 2005: 107-117 [doi]

Extracting Speedup From C-Code With Poor Instruction-Level ParallelismDara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster. ipps 2005: [doi]

2004

A 64-way VLIW/SIMD FPGA architecture and design flowAlex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh. icecsys 2004: 499-502 [doi]

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