Jude A. Rivers - researchr alias

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2011

Error Tolerance in Server Class ProcessorsJude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose. tcad, 30(7):945-959, 2011. [doi]

2010

2009

Tribeca: design for PVT variations with local recovery and fine-grained adaptationMeeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks. micro 2009: 435-446 [doi]

Scalable high performance main memory system using phase-change memory technologyMoinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers. isca 2009: 24-33 [doi]

Reliability Challenges and System Performance at the Architecture LevelJude A. Rivers, Prabhakar Kudva. dt, 26(6):62-73, 2009. [doi]

2008

2007

Architecture-Level Soft Error Analysis: Examining the Limits of Common AssumptionsXiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers. dsn 2007: 266-275 [doi]

A Framework for Architecture-Level Lifetime Reliability ModelingJeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose. dsn 2007: 534-543 [doi]

2005

2004

The Impact of Technology Scaling on Lifetime ReliabilityJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. dsn 2004: 177 [doi]

The Case for Lifetime Reliability-Aware MicroprocessorsJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. isca 2004: 276-287 [doi]

2003

Reducing instruction fetch energy with backwards branch control information and bufferingJude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno. islped 2003: 322-325 [doi]

1999

Active Management of Data Caches by Exploiting Reuse InformationEdward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson. TC, 48(11):1244-1259, 1999. [doi]

1998

Utilizing Reuse Information in Data Cache ManagementJude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens. ics 1998: 449-456 [doi]

mlcache: A Flexible Multi-Lateral Cache SimulatorEdward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson. mascots 1998: 19-26 [doi]

1997

On High-Bandwidth Data Cache Design for Multi-Issue ProcessorsJude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin. euromicro 1997: 46-56 [doi]

On Effective Data Supply For Multi-Issue ProcessorsJude A. Rivers, Edward S. Tam, Edward S. Davidson. iccd 1997: 519-528

1996

Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based DesignJude A. Rivers, Edward S. Davidson. icpp 1996: 154-163

Performance Issues in Integrating Temporality-Based Caching with PrefetchingJude A. Rivers, Edward S. Davidson. pe, 27/28(4):189-207, 1996.