Junji Kitamichi - researchr alias

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Viewing Publication 1 - 22 from 22

2016

Proposing a Highly Reliable Real-Time Operating System for a Processor with a Fault Self-Detecting MechanismHiroki Saito, Yoichi Tomioka, Junji Kitamichi. icess 2016: 164-169 [doi]

2015

On-demand Customizable Wireless Sensor NetworkToshiaki Miyazaki, Peng Li, Song Guo, Junji Kitamichi, Takafumi Hayashi, Tsuneo Tsukahara. ant 2015: 302-309 [doi]

2014

2013

Programmable wireless sensor node featuring low-power FPGA and microcontrollerShoichi Yamaguchi, Toshiaki Miyazaki, Junji Kitamichi, Song Guo 0001, Tsuneo Tsukahara, Takafumi Hayashi. icawst 2013: 596-601 [doi]

Evolution of Software-Defined Sensor NetworksDeze Zeng, Toshiaki Miyazaki, Song Guo, Tsuneo Tsukahara, Junji Kitamichi, Takafumi Hayashi. msn 2013: 410-413 [doi]

2008

2007

Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable SystemsKenji Asano, Junji Kitamichi, Kenichi Kuroda. vlsid 2007: 373-378 [doi]

A Hardware Algorithm for the Minimum p-Quasi Clique Cover ProblemShuichi Watanabe, Junji Kitamichi, Kenichi Kuroda. fpl 2007: 139-144 [doi]

2005

A Master-Slave Adaptive Load-Distribution Processor Model on PCAToshiyuki Ito, Junji Kitamichi, Kenichi Kuroda, Yuichi Okuyama. ipps 2005: [doi]

2001

A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMsAtsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino, Ana R. Cavalli. icoin 2001: 155-162 [doi]

1999

A gradual neural network approach for FPGA segmented channel routing problemsNobuo Funabiki, M. Yoda, Junji Kitamichi, Seishi Nishikawa. tsmc, 29(4):481-489, 1999.

Formal Verification Method for Combinatorial Circuits at High Level DesignJunji Kitamichi, Hiroyuki Kageyama, Nobuo Funabiki. aspdac 1999: 319 [doi]

Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction ExecutionTakashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi. aspdac 1999: 177-180 [doi]

1998

A three-stage greedy and neural-network approach for the subgraph isomorphism problemNobuo Funabiki, Junji Kitamichi. SMC 1998: 1892-1897 [doi]

An evolutionary neural network approach for module orientation problemsNobuo Funabiki, Junji Kitamichi, Seishi Nishikawa. tsmc, 28(6):849-855, 1998.

A gradual neural-network algorithm for jointly time-slot/code assignment problems in packet radio networksNobuo Funabiki, Junji Kitamichi. tnn, 9(6):1523-1528, 1998. [doi]

1997

An evolutionary neural network algorithm for max cut problemsNobuo Funabiki, Junji Kitamichi, Seishi Nishikawa. icnn 1997: 1260-1265 [doi]

1994

Hardware synthesis from a restricted class of LOTOS expressionsTeruo Higashino, Keiichi Yasumoto, Junji Kitamichi, Kenichi Taniguchi. pstv 1995: 379-386

Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic ApproachJunji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi. tpcd 1994: 165-184

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