Karthikeyan Lingasubramanian - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 14 from 14

2020

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation studyVarsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan. peerj-cs, 6, 2020. [doi]

2019

Effect of sign-bit-flipping trojan on turbo coded communication systemsKarthi Balasubramanian, B. Yamuna, Salija P, Karthikeyan Lingasubramanian, Deepak Mishra. icdcn 2019: 502-505 [doi]

2018

Study of hardware trojans based security vulnerabilities in cyber physical systemsKarthikeyan Lingasubramanian, Ranveer Kumar, Nagendra Babu Gunti, Thomas Morris. iccel 2018: 1-6 [doi]

2017

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated CircuitsGunti Nagendra Babu, Karthikeyan Lingasubramanian. integration, 59:233-242, 2017. [doi]

Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMRNagendra Babu Gunti, Karthikeyan Lingasubramanian. ifip5-5 2017: 99-104 [doi]

Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy SchemeNagendra Babu Gunti, Karthikeyan Lingasubramanian. ifip5-5 2017: 105-110 [doi]

2014

Realizing a security aware triple modular redundancy scheme for robust integrated circuitsGunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian. vlsi 2014: 1-6 [doi]

2011

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesisKarthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja. mr, 51(2):485-501, 2011. [doi]

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-GatingKarthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. patmos 2011: 214-225 [doi]

2009

An Error Model to Study the Behavior of Transient Errors in Sequential CircuitsKarthikeyan Lingasubramanian, Sanjukta Bhanja. vlsid 2009: 485-490 [doi]

Probabilistic Error Modeling for Nano-Domain Logic CircuitsThara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja. tvlsi, 17(1):55-65, 2009. [doi]

2007

Probabilistic maximum error modeling for unreliable logic circuitsKarthikeyan Lingasubramanian, Sanjukta Bhanja. glvlsi 2007: 223-226 [doi]

2006

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networksSanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan. todaes, 11(3):773-796, 2006. [doi]

2005

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian NetworksSanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan. vlsid 2005: 586-591 [doi]

Sign in or sign up to see more results.

runs on WebDSL