Kaushik Roy - researchr alias

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2011

Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 VIk Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy. tvlsi, 19(8):1429-1437, 2011. [doi]

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video ApplicationsIk Joon Chang, Debabrata Mohapatra, Kaushik Roy. tcsv, 21(2):101-112, 2011. [doi]

Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive ClockingSwaroop Ghosh, Kaushik Roy. tvlsi, 19(8):1504-1507, 2011. [doi]

IMPACT: imprecise adders for low-power approximate computingVaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy. islped 2010: 409-414 [doi]

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displaysChih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy. aspdac 2011: 695-700 [doi]

Scaled LTPS TFTs for low-cost low-power applicationsSoo Youn Kim, Selin Baytok, Kaushik Roy. isqed 2011: 745-750 [doi]

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell ArrayJaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy. tvlsi, 19(9):1727-1730, 2011. [doi]

Memory-based embedded digital ATEDongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy. vts 2011: 266-271 [doi]

Viterbi-Based Efficient Test Data CompressionDongsoo Lee, Kaushik Roy. ets 2011: 204 [doi]

Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processorsSang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy. islped 2010: 303-308 [doi]

2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI ToleranceYiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy. tvlsi, 18(11):1621-1624, 2010. [doi]

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiencyVinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar. dac 2010: 555-560 [doi]

Improved clock-gating control scheme for transparent pipelineJung Hwan Choi, Byung-Guk Kim, Aurobindo Dasgupta, Kaushik Roy. aspdac 2010: 401-406 [doi]

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input SwitchingSeung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy. tcad, 29(3):497-502, 2010. [doi]

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive ClockingSwaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy. tvlsi, 18(9):1301-1309, 2010. [doi]

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architectureVaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy. iccd 2010: 260-265 [doi]

ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage ScalingMyeong-Eun Hwang, Kaushik Roy. tvlsi, 18(2):281-290, 2010. [doi]

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing FailuresKunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy. tvlsi, 18(2):270-280, 2010. [doi]

A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement techniqueGeorgios Karakonstantis, Charles Augustine, Kaushik Roy. iolts 2010: 3-8 [doi]

HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offsGeorgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy. islped 2010: 117-122 [doi]

Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power ComputingGeorgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy. tvlsi, 18(10):1461-1470, 2010. [doi]

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture PerspectiveJing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy. tvlsi, 18(12):1710-1723, 2010. [doi]

Efficient power conversion for ultra low voltage micro scale energy transducersChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. date 2010: 1602-1607 [doi]

Maximum power point considerations in micro-scale solar energy harvesting systemsChao Lu, Vijay Raghunathan, Kaushik Roy. iscas 2010: 273-276 [doi]

Micro-scale energy harvesting: a system design perspectiveChao Lu, Vijay Raghunathan, Kaushik Roy. aspdac 2010: 89-94 [doi]

Analysis and design of ultra low power thermoelectric energy harvesting systemsChao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy. islped 2010: 183-188 [doi]

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detectionHimanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy. islped 2010: 301-306 [doi]

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature VariationsMesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy. tcad, 29(1):2-13, 2010. [doi]

Self-Repairing SRAM Using On-Chip Detection and CompensationNiladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy. tvlsi, 18(1):75-84, 2010. [doi]

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection ApproachSeetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia. host 2010: 13-18 [doi]

Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical PathsPatrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy. tvlsi, 18(1):53-65, 2010. [doi]

A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance ProcessorsPatrick Ndai, Ashish Goel, Kaushik Roy. tvlsi, 18(8):1209-1219, 2010. [doi]

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation EnergyJongsun Park, Jung Hwan Choi, Kaushik Roy. tvlsi, 18(5):787-793, 2010. [doi]

Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous ComponentsKaushik Roy, Byunghoo Jung, Anand Raghunathan. vlsid 2010: 464-469 [doi]

Word-Wise Handwritten Persian and Roman Script IdentificationKaushik Roy, Alireza Alaei, Umapada Pal. icfhr 2010: 628-633 [doi]

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysisElena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras. ets 2010: 69-74 [doi]

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive FilteringYongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy. vlsisp, 58(2):125-137, 2010. [doi]

2009

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devicesCharles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy. isqed 2009: 80-85 [doi]

A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systemsCharles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy. aspdac 2009: 847-852 [doi]

Coping with Variations through System-Level DesignNilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy. vlsid 2009: 581-586 [doi]

Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation FilteringNilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy. tcad, 28(8):1127-1137, 2009. [doi]

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processorsIk Joon Chang, Debabrata Mohapatra, Kaushik Roy. dac 2009: 670-675 [doi]

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled TechnologiesYiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh. tvlsi, 17(12):1749-1752, 2009. [doi]

Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR FiltersJung Hwan Choi, Nilanjan Banerjee, Kaushik Roy. tcad, 28(1):87-97, 2009. [doi]

Impact of SoC power management techniques on verification and testingBhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d Abreu. isqed 2009: 692-695 [doi]

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuningGeorgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy. sips 2009: 133-138 [doi]

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost ApplicationsJing Li, Kunhyuk Kang, Kaushik Roy. tcad, 28(1):46-59, 2009. [doi]

An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspectiveJing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy. aspdac 2009: 841-846 [doi]

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock GatingHamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy. tvlsi, 17(1):33-44, 2009. [doi]

Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variationsMesut Meterelliyoz, Kaushik Roy. aspdac 2009: 787-792 [doi]

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimatorDebabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy. islped 2009: 195-200 [doi]

Indian Multi-Script Full Pin-code String Recognition for Postal AutomationUmapada Pal, Rami Kumar Roy, Kaushik Roy, Fumitaka Kimura. icdar 2009: 456-460 [doi]

A Lexicon-Driven Handwritten City-Name Recognition Scheme for Indian Postal AutomationUmapada Pal, Kaushik Roy, Fumitaka Kimura. ieicet, 92-D(5):1146-1158, 2009. [doi]

Reliability Implications of Bias-Temperature Instability in Digital ICsSang Phill Park, Kunhyuk Kang, Kaushik Roy. dt, 26(6):8-17, 2009. [doi]

Device/circuit interactions at 22nm technology nodeKaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta. dac 2009: 97-102 [doi]

Ultra low voltage CMOSKaushik Roy. islped 2009: 425-426 [doi]

2008

Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing SystemsNilanjan Banerjee, Charles Augustine, Kaushik Roy. dft 2008: 323-331 [doi]

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate TechnologiesAditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy. vlsid 2008: 125-130 [doi]

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating TechniqueSwarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy. et, 24(6):577-590, 2008. [doi]

Low power design under parameter variationsSwarup Bhunia, Kaushik Roy. socc 2008: 389-390 [doi]

Low power design under parameter variationsSwarup Bhunia, Kaushik Roy. islped 2008: 137-138 [doi]

Profit Aware Circuit Design Under Process Variations Considering Speed BinningAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy. tvlsi, 16(7):806-815, 2008. [doi]

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretchingSwaroop Ghosh, Kaushik Roy. aspdac 2008: 635-640 [doi]

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive ClockingSwaroop Ghosh, Patrick Ndai, Kaushik Roy. date 2008: 366-371 [doi]

O:::2:::C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessorsSwaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy. islped 2008: 189-192 [doi]

Power-Aware Testing and Test Strategies for Low Power DevicesDimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen. date 2008: [doi]

Soft Errors: System Effects, Protection Techniques and Case StudiesDimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda. date 2008: [doi]

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy. aspdac 2008: 726-731 [doi]

Tutorial: SoC Power Management Verification and Testing IssuesBhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy. mtv 2008: 67-72 [doi]

Process variation tolerant SRAM array for ultra low voltage applicationsJaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy. dac 2008: 108-113 [doi]

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTsJing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy. jetc, 4(3), 2008. [doi]

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancementJing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy. dac 2008: 278-283 [doi]

Thermal analysis of 8-T SRAM for nano-scaled technologiesMesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy. islped 2008: 123-128 [doi]

Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation CircuitryNiladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy. vts 2008: 101-106 [doi]

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body BiasSaibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy. tcad, 27(1):174-183, 2008. [doi]

Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved ThroughputPatrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy. TC, 57(7):940-951, 2008. [doi]

A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power ConsumptionJongsun Park, Kaushik Roy. vlsisp, 53(3):399-410, 2008. [doi]

Optimal Features Subset Selection Using Genetic Algorithms for Iris RecognitionKaushik Roy, Prabir Bhattacharya. iciar 2008: 894-904 [doi]

Improving Features Subset Selection Using Genetic Algorithms for Iris RecognitionKaushik Roy, Prabir Bhattacharya. annpr 2008: 292-304 [doi]

Trilingual Script Separation of Handwritten Postal DocumentKaushik Roy, Kinshuk Majumder. icvgip 2008: 693-700 [doi]

Adaptive asymmetrical SVM and genetic algorithms based iris recognitionKaushik Roy, Prabir Bhattacharya. icpr 2008: 1-4 [doi]

2007

A process variation aware low power synthesis methodology for fixed-point FIR filtersNilanjan Banerjee, Jung Hwan Choi, Kaushik Roy. islped 2007: 147-152 [doi]

Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal ProcessingNilanjan Banerjee, Kaushik Roy. jolpe, 3(3):254-270, 2007. [doi]

The effect of process variation on device temperature in FinFET circuitsJung Hwan Choi, Jayathi Murthy, Kaushik Roy. iccad 2007: 747-751 [doi]

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path IsolationSwaroop Ghosh, Swarup Bhunia, Kaushik Roy. tcad, 26(11):1947-1956, 2007. [doi]

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage schedulingSwaroop Ghosh, Swarup Bhunia, Kaushik Roy. date 2007: 1532-1537 [doi]

Tolerance to Small Delay Defects by Adaptive Clock StretchingSwaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy. iolts 2007: 244-252 [doi]

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scalingMyeong-Eun Hwang, Tamer Cakici, Kaushik Roy. date 2007: 1550-1555 [doi]

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gatesMyeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy. islped 2007: 387-390 [doi]

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performanceKunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam. iccad 2007: 730-734 [doi]

Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ MeasurementKunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy. dac 2007: 358-363 [doi]

A low-power SRAM using bit-line charge-recycling techniqueKeejong Kim, Hamid Mahmoodi, Kaushik Roy. islped 2007: 177-182 [doi]

A High Performance, Scalable Multiplexed Keeper TechniqueJaydeep P. Kulkarni, Kaushik Roy. isqed 2007: 545-549 [doi]

High Performance and Low Power Electronics on Flexible SubstrateJing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy. dac 2007: 274-275 [doi]

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devicesSaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy. mj, 38(8-9):931-941, 2007. [doi]

Fine-Grained Redundancy in AddersPatrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy. isqed 2007: 317-321 [doi]

Collarette Area Localization and Asymmetrical Support Vector Machines for Efficient Iris RecognitionKaushik Roy, Prabir Bhattacharya. iciap 2007: 3-8 [doi]

A New Hybrid State Estimator for Systems with Limited Mode ChangesKaushik Roy, Claire Tomlin. hybrid 2007: 487-500 [doi]

Application of Multi-objective Genetic Algorithm and asymmetrical Support Vector Machine to improve the reliability of an iris recognition systemKaushik Roy, Prabir Bhattacharya. SMC 2007: 1952-1957 [doi]

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select AddersHiroaki Suzuki, Woopyo Jeong, Kaushik Roy. ieicet, 90-C(4):865-876, 2007. [doi]

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