Kaustav Banerjee - researchr alias

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Viewing Publication 1 - 68 from 68

2023

Exploration and Exploitation of Strain Engineering in 2D-FETsAnkit Kumar, Arnab Pal, Kamyar Parto, Wei Cao, Kaustav Banerjee. drc 2023: 1-2 [doi]

2020

Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability"Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee. tcad, 39(1):277, 2020. [doi]

2013

2D electronics: Graphene and beyondWei Cao, Jiahao Kang, Wei Liu, Yasin Khatami, Deblina Sarkar, Kaustav Banerjee. essderc 2013: 37-44 [doi]

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and ReliabilityChuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee. tcad, 32(7):1045-1058, 2013. [doi]

2012

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple SubstratesChuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee. tcad, 31(11):1698-1710, 2012. [doi]

2010

Aging-resilient design of pipelined architectures using novel detection and correction circuitsHamed F. Dadgour, Kaustav Banerjee. date 2010: 244-249 [doi]

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMsHamed F. Dadgour, Muhammad M. Hussain, Kaustav Banerjee. islped 2010: 7-12 [doi]

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or GatesHamed F. Dadgour, Kaustav Banerjee. tvlsi, 18(11):1567-1577, 2010. [doi]

Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMSHamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee. dac 2010: 893-896 [doi]

Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICsHong Li, Chuan Xu, Kaustav Banerjee. dt, 27(4):20-31, 2010. [doi]

Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital designSeid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee. iccad 2010: 714-720 [doi]

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrateNavin Srivastava, Roberto Suaya, Kaustav Banerjee. date 2010: 459-464 [doi]

Corrections to Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate [Jul 09 1047-1060]Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee. tcad, 29(5):849, 2010. [doi]

2009

Graphene based nanomaterials for VLSI interconnect and energy-storage applicationsKaustav Banerjee. slip 2009: 105-106 [doi]

Graphene based transistors: physics, status and future perspectivesKaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli. ispd 2009: 65-66 [doi]

Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designsHamed F. Dadgour, Kaustav Banerjee. iet-cdt, 3(6):593-608, 2009. [doi]

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantizationSeid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee. iccad 2009: 505-512 [doi]

High-speed low-power FinFET based domino logicSeid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee. aspdac 2009: 829-834 [doi]

Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologiesChuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard Smith, Kaustav Banerjee. iccad 2009: 658-665 [doi]

2008

2007

2006

Are carbon nanotubes the future of VLSI interconnections?Kaustav Banerjee, Navin Srivastava. dac 2006: 809-814 [doi]

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systemsKaustav Banerjee, Sheng-Chih Lin, Navin Srivastava. aspdac 2006: 223-230 [doi]

Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?Kaustav Banerjee, Sungjun Im, Navin Srivastava. nanonet 2006: 1-9 [doi]

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gatesHamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee. dac 2006: 977-982 [doi]

Tutorial 1: Emerging Technologies for VLSI DesignRajiv V. Joshi, Kaustav Banerjee, André DeHon. isqed 2006: 4 [doi]

An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot managementSheng-Chih Lin, Kaustav Banerjee. iccad 2006: 568-574 [doi]

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchyGian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee. dac 2006: 991-996 [doi]

Introspective 3D chipsShashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood. asplos 2006: 264-273 [doi]

2005

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnectsAmir H. Ajami, Kaustav Banerjee, Massoud Pedram. tcad, 24(6):849-861, 2005. [doi]

Plenary Session 2PLech Józwiak, Kaustav Banerjee. isqed 2005: 461 [doi]

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICsSheng-Chih Lin, Navin Srivastava, Kaustav Banerjee. iccd 2005: 411-416 [doi]

Supply and power optimization in leakage-dominant technologiesMan Lung Mui, Kaustav Banerjee, Amit Mehrotra. tcad, 24(9):1362-1371, 2005. [doi]

Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated CircuitsNavin Srivastava, Xiaoning Qi, Kaustav Banerjee. isqed 2005: 346-351 [doi]

Performance analysis of carbon nanotube interconnects for VLSI applicationsNavin Srivastava, Kaustav Banerjee. iccad 2005: 383-390

A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variationsVineet Wason, Kaustav Banerjee. islped 2005: 131-136 [doi]

2004

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant eraAnirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee. dac 2004: 884-887 [doi]

A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot ArrayAnirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee. isqed 2004: 259-264 [doi]

Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designsAdil Koukab, Kaustav Banerjee, Michel J. Declercq. tcad, 23(6):823-836, 2004. [doi]

Power Supply Optimization in sub-130 nm Leakage Dominant Technologies Man Lung Mui, Kaustav Banerjee, Amit Mehrotra. isqed 2004: 409-414 [doi]

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variationsSongqing Zhang, Vineet Wason, Kaustav Banerjee. islped 2004: 156-161 [doi]

2003

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated CircuitsSantanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu. iccad 2003: 497-503 [doi]

Nano, quantum, and molecular computing: are we ready for the validation and test challenges?Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu. hldvt 2003: 3-7 [doi]

2002

Inductance Aware Interconnect ScalingKaustav Banerjee, Amit Mehrotra. isqed 2002: 43-47 [doi]

Analysis of on-chip inductance effects for distributed RLC interconnectsKaustav Banerjee, Amit Mehrotra. tcad, 21(8):904-915, 2002. [doi]

Few electron devices: towards hybrid CMOS-SET integrated circuitsAdrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier. dac 2002: 88-93 [doi]

Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate ArchitectureAdrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, P. Renaud, C. Hibert, Philippe Flückiger, G. A. Racine. isqed 2002: 496-501 [doi]

Analysis and optimization of substrate noise coupling in single-chip RF transceiver designAdil Koukab, Kaustav Banerjee, Michel J. Declercq. iccad 2002: 309-316 [doi]

A SET quantizer circuit aiming at digital communication systemSantanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq. iscas 2002: 860-863 [doi]

2001

Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICsAmir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken. dac 2001: 567-572 [doi]

Effects of non-uniform substrate temperature on the clock signal integrity in high performance designsAmir H. Ajami, Massoud Pedram, Kaustav Banerjee. cicc 2001: 233-236 [doi]

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer InsertionAmir H. Ajami, Kaustav Banerjee, Massoud Pedram. iccad 2001: 44-48 [doi]

Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC InterconnectsKaustav Banerjee, Amit Mehrotra. dac 2001: 798-803 [doi]

Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal NetsKaustav Banerjee, Amit Mehrotra. iccad 2001: 158-164 [doi]

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integrationKaustav Banerjee, Shukri J. Souri, Pawan Kapur, Krishna C. Saraswat. pieee, 89(5):602-633, 2001. [doi]

Analysis and optimization of thermal issues in high-performance VLSIKaustav Banerjee, Massoud Pedram, Amir H. Ajami. ispd 2001: 230-237 [doi]

Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI InterconnectsTingYen Chiang, Kaustav Banerjee, Krishna Saraswat. iccad 2001: 165 [doi]

Interconnect limits on gigascale integration (GSI) in the 21st centuryJeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl. pieee, 89(3):305-324, 2001. [doi]

Analysis and Design of ESD Protection Circuits for High-Frequency/RF ApplicationsChoshu Ito, Kaustav Banerjee, Robert W. Dutton. isqed 2001: 117-122 [doi]

A fast analytical technique for estimating the bounds of on-chip clock wire inductanceYi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton. cicc 2001: 241-244 [doi]

2000

Performance analysis and technology of 3-D ICsKrishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur. slip 2000: 85-90 [doi]

Multiple Si layer ICs: motivation, performance analysis, and design implicationsShukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat. dac 2000: 213-220 [doi]

1999

On Thermal Effects in Deep Sub-Micron VLSI InterconnectsKaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu. dac 1999: 885-891 [doi]

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