Kazuaki Murakami - researchr alias

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2011

A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuitsFarhad Mehdipour, Hiroaki Honda, Koji Inoue, Hiroshi Kataoka, Kazuaki Murakami. jsa, 57(1):169-179, 2011. [doi]

2010

Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuitsFarhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki Murakami, Hiroyuki Akaike, Akira Fujimaki. date 2010: 993-996 [doi]

2009

A Dynamic Solution for Efficient MPI Collective CommunicationsHyacinthe Nzigou Mamadou, Feng Long Gu, Vivien Oddou, Takeshi Nanri, Kazuaki Murakami. cso 2009: 3-7 [doi]

Rapid Design Space Exploration of a Reconfigurable Instruction-Set ProcessorFarhad Mehdipour, Hamid Noori, Koji Inoue, Kazuaki Murakami. ieicet, 92-A(12):3182-3192, 2009. [doi]

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processorFarhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami. aspdac 2009: 564-569 [doi]

Reducing On-Chip DRAM Energy via Data Transfer Size OptimizationTakatsugu Ono, Koji Inoue, Kazuaki Murakami, Kenji Yoshida. ieicet, 92-C(4):433-443, 2009. [doi]

Empirical Performance Models for Java WorkloadsPradeep Rao, Kazuaki Murakami. arcs 2009: 219-232 [doi]

Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java BytecodePradeep Rao, Kazuaki Murakami. ieicet, 92-C(10):1265-1275, 2009. [doi]

Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional UnitsAntoine Trouve, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki Murakami. reconfig 2009: 231-236 [doi]

2008

Performance Models for MPI Collective Communications with Network ContentionHyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami. ieicet, 91-B(4):1015-1024, 2008. [doi]

Design space exploration for a coarse grain acceleratorFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami. aspdac 2008: 685-690 [doi]

A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom InstructionsHamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami. ieicet, 91-C(4):497-508, 2008. [doi]

Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration SelectionHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. isvlsi 2008: 363-368 [doi]

Temperature-Aware Configurable Cache to Reduce Energy in Embedded SystemsHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. ieicet, 91-C(4):418-431, 2008. [doi]

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extensionHamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami. islped 2008: 241-246 [doi]

An architecture framework for an adaptive extensible processorHamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani. tjs, 45(3):313-340, 2008. [doi]

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection SystemsMakoto Sugihara, Yusuke Matsunaga, Kazuaki Murakami. ieicet, 91-A(12):3451-3460, 2008. [doi]

Reliable Cache Architectures and Task Scheduling for Multiprocessor SystemsMakoto Sugihara, Tohru Ishihara, Kazuaki Murakami. ieicet, 91-C(4):410-417, 2008. [doi]

Performance prediction of large-scale parallell system and application using macro-level simulationRyutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu. sc 2008: 20 [doi]

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum CircuitsNaofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda. ieicet, 91-C(3):350-355, 2008. [doi]

2007

Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication AlgorithmsHyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami, Guilherme de Melo Baptista Domingues. sbac-pad 2007: 203-210 [doi]

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow GraphsFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami. ieicet, 90-D(12):1956-1966, 2007. [doi]

Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processorHamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi. date 2007: 325-330 [doi]

The effect of temperature on cache size tuning for low energy embedded systemsHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. glvlsi 2007: 453-456 [doi]

The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded SystemsHamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami. csreaESA 2007: 169-176

Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable AcceleratorHamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami. icess 2007: 249-260 [doi]

A Next-Generation Enterprise Server System with Advanced Cache Coherence ChipsMariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki Murakami. ieicet, 90-C(10):1972-1982, 2007. [doi]

Dynamic Optimization of Load Balance in MPI BroadcastTakesi Soga, Kouji Kurihara, Takeshi Nanri, Motoyoshi Kurokawa, Kazuaki Murakami. pvm 2007: 387-388 [doi]

Technology Mapping Technique for Increasing Throughput of Character Projection LithographyMakoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki Murakami. ieicet, 90-C(5):1012-1020, 2007. [doi]

Task scheduling for reliable cache architectures of multiprocessor systemsMakoto Sugihara, Tohru Ishihara, Kazuaki Murakami. date 2007: 1490-1495 [doi]

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer SystemsMakoto Sugihara, Tohru Ishihara, Kazuaki Murakami. ieicet, 90-C(10):1983-1991, 2007. [doi]

2006

REDEFIS: a system with a redefinable instruction set processorVictor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami. sbcci 2006: 14-19 [doi]

Circuit Area-latency Optimization Technique for High-precision Elementary FunctionsKoji Hashimoto, Vasily G. Moshnyaga, Kazuaki Murakami. apccas 2006: 1406-1409 [doi]

Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBandHyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki Murakami. hipc 2006: 547-559 [doi]

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional UnitFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi. euc 2006: 722-731 [doi]

An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional UnitFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue. APCSAC 2006: 219-230 [doi]

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design frameworkFarhad Mehdipour, Morteza Saheb Zamani, H. R. Ahmadifar, Mehdi Sedighi, Kazuaki Murakami. ipps 2006: [doi]

GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow GraphsFarhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori. ersa 2006: 227-230

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible ProcessorHamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani. fpl 2006: 1-4 [doi]

Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applicationsHamid Noori, Kazuaki Murakami. SAC 2006: 937-938 [doi]

Cell Library Development Methodology for Throughput Enhancement of Character Projection EquipmentMakoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura. ieicet, 89-C(3):377-383, 2006. [doi]

A character size optimization technique for throughput enhancement of character projection lithographyMakoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura. iscas 2006: [doi]

2005

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data CachesReiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami. ieicet, 88-A(4):862-868, 2005. [doi]

2004

Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning ConstraintsMakoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga. isvlsi 2004: 179-186 [doi]

2002

2001

Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communicationTakanori Okuma, Koji Hashimoto, Kazuaki Murakami. aspdac 2001: 37-38 [doi]

2000

Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory SystemsKoji Inoue, Koji Kai, Kazuaki Murakami. ims 2001: 169-178 [doi]

1999

Way-predicting set-associative cache for high performance and low energy consumptionKoji Inoue, Tohru Ishihara, Kazuaki Murakami. islped 1999: 273-275 [doi]

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIsKoji Inoue, Koji Kai, Kazuaki Murakami. hpca 1999: 218-222 [doi]

1998

Optimizing the DRAM refresh count for merged DRAM/logic LSIsTaku Ohsawa, Koji Kai, Kazuaki Murakami. islped 1998: 82-87 [doi]

1993

A Micro-Vectorprocessor Architecture: Performance Modeling and BenchmarkingTakashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura. ics 1993: 308-317 [doi]

1992

Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architectureTetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita. ics 1992: 272-281 [doi]

1989