Kiran V. Chatty - researchr alias

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2010

Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodologyT. Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier. mr, 50(9-11):1367-1372, 2010. [doi]

2009

2007

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICsCiaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier. mr, 47(7):1030-1035, 2007. [doi]

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICsCiaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier. mr, 47(7):1069-1073, 2007. [doi]

2006

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implantD. Alvarez, M. J. Abou-Khalil, C. Russ, Kiran V. Chatty, Robert Gauthier, D. Kontos, J. Li, C. Seguin, R. Halbach. mr, 46(9-11):1597-1602, 2006. [doi]

2003