Kyomin Sohn - researchr alias

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Viewing Publication 1 - 31 from 31

2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QECTaeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. vlsit 2023: 1-2 [doi]

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/sJi-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. jssc, 58(11):3242-3252, November 2023. [doi]

2022

An Architecture of Sparse Length Sum Accelerator in AxDIMMShinhaeng Kang, Byeongho Kim, Sukhan Lee 0002, Kyomin Sohn. aicas 2022: 1-4 [doi]

An FPGA-based RNN-T Inference Accelerator with PIM-HBMShinhaeng Kang, Sukhan Lee 0002, Byeongho Kim, Hweesoo Kim, Kyomin Sohn, Nam Sung Kim, Eojin Lee. fpga 2022: 146-152 [doi]

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBMJi-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. vlsit 2022: 152-153 [doi]

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked ICJi-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Sunghwan Jo, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung. jssc, 57(6):1913-1923, 2022. [doi]

Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration BufferJin Hyun Kim, Shinhaeng Kang, Sukhan Lee 0002, Hyeonsu Kim, Yuhwan Ro, SeungWon Lee, David Wang 0003, JiHyun Choi, Jinin So, YeonGon Cho, Joon Ho Song, Jeonghyeon Cho, Kyomin Sohn, Nam Sung Kim. micro, 42(3):20-30, 2022. [doi]

2021

HBM3 RAS: Enhancing Resilience at ScaleSudhanva Gurumurthi, Kijun Lee, Munseon Jang, Vilas Sridharan, Aaron Nygren, Yesin Ryu, Kyomin Sohn, Taekyun Kim, Hoeju Chung. cal, 20(2):158-161, 2021. [doi]

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial ProductSuk-Han Lee, Shinhaeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, SeungWon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim. isca 2021: 43-56 [doi]

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM ProcessJaewon Park, Jae-Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang. access, 9:33487-33497, 2021. [doi]

2020

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2016

2013

2012

2008

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block RedundancyKyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim. isscc 2008: 386-387 [doi]

2007

An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAMHyejung Kim, Kyomin Sohn, Jerald Yoo, Hoi-Jun Yoo. cicc 2007: 787-790 [doi]

2006

A Multi-Nodes Human Body Communication Sensor Network Control ProcessorSungdae Choi, Seong-Jun Song, Kyomin Sohn, Hyejung Kim, Joo-Young Kim, Namjun Cho, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo. cicc 2006: 109-112 [doi]

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human BodySungdae Choi, Seong-Jun Song, Kyomin Sohn, Hyejung Kim, Jooyoung Kim, Jerald Yoo, Hoi-Jun Yoo. iiswc 2006: 139-140 [doi]

An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node ControlSungdae Choi, Kyomin Sohn, Hyejung Kim, Joo-Young Kim 0001, Seong-Jun Song, Namjun Cho, Jerald Yoo, Hoi-Jun Yoo. issoc 2006: 1-4 [doi]

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technologyKyomin Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo. jssc, 41(4):823-830, 2006. [doi]

2005

A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architectureSungdae Choi, Kyomin Sohn, Hoi-Jun Yoo. jssc, 40(1):254-260, 2005. [doi]

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