Leendert M. Huisman - researchr alias

researchr

You are not signed in
Sign in
Sign up

2004

Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)Leendert M. Huisman. tcad, 23(1):91-101, 2004. [doi]

Data Mining Integrated Circuit Fails with Fail CommonalitiesLeendert M. Huisman, Maroun Kassab, Leah Pastel. itc 2003: 661-668 [doi]

2003

Analysis and Design of Optimal Combinational CompactorsPeter Wohl, Leendert M. Huisman. vts 2003: 101-106 [doi]

2001

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigmThomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski. itc 2001: 287-296

1998

Correlations between path delays and the accuracy of performance predictionLeendert M. Huisman. itc 1998: 801-808 [doi]

Diagnosis and characterization of timing-related defects by time-dependent light emissionDaniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika. itc 1998: 733-739 [doi]

1995

Yield fluctuations and defect modelsLeendert M. Huisman. et, 7(3):241-254, 1995. [doi]

1994

Highly Reliable Symmetric NetworksLeendert M. Huisman, Sandip Kundu. tpds, 5(1):94-97, 1994. [doi]

The Effect on Quality of Non-Uniform Fault Coverage and Fault ProbabilityPeter C. Maxwell, Robert C. Aitken, Leendert M. Huisman. itc 1994: 739-746

1992

A Small Test Generator for Large DesignsSandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy. itc 1992: 30-40

1988

SLS-a fast switch-level simulator [for MOS]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman. tcad, 7(8):838-849, 1988. [doi]

TRIM: testability range by ignoring the memoryLarry Carter, Leendert M. Huisman, Tom W. Williams. tcad, 7(1):38-49, 1988. [doi]

1986

SLS - a fast switch level simulator for verification and fault coverage analysisZeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman. dac 1986: 164-170 [doi]

TRIM : Testability Range by Ignoring the MemoryLeendert M. Huisman, Larry Carter, Tom W. Williams. itc 1986: 474-479

1984

Using a Hardware Simulation Engine for Custom MOS Structured DesignsZeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman. ibmrd, 28(5):564-571, 1984.