Madhav P. Desai - researchr alias

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Viewing Publication 1 - 33 from 33

2022

Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture ExplorationNeha V. Karanjkar, Madhav P. Desai. simultech 2022: 142-150 [doi]

2018

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technologyNanditha P. Rao, Madhav P. Desai. mj, 72:86-99, 2018. [doi]

2016

Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate ArrayKartik Lakhotia, Gabriel Caffarena, Alberto Gil, David G. Márquez, Abraham Otero, Madhav P. Desai. iwbbio 2016: 266-276 [doi]

2015

An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation TechniqueNeha V. Karanjkar, Madhav P. Desai. mascots 2015: 85-88 [doi]

A Detailed Characterization of Errors in Logic Circuits due to Single-Event TransientsNanditha P. Rao, Madhav P. Desai. dsd 2015: 714-721 [doi]

2012

The Click2NetFPGA ToolchainTeemu Rinta-aho, Mika Karlstedt, Madhav P. Desai. usenix 2012: 77-88 [doi]

2010

Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory SystemsGautam Hazari, Madhav P. Desai, G. Srinivas. vlsid 2010: 15-20 [doi]

A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital SystemsSameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai. dsd 2010: 147-154 [doi]

2009

Learning based address mapping for improving the performance of memory subsystemsPratyush Kumar, Madhav P. Desai. mascots 2009: 1-9 [doi]

2007

On the Impact of Address Space Assignment on Performance in Systems-on-ChipG. Hazari, Madhav P. Desai, H. Kasture. vlsid 2007: 540-545 [doi]

AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level ProgramsSameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai. vlsid 2007: 245-250 [doi]

Parallelization of DC Analysis through Multiport DecompositionGaurav Trivedi, Madhav P. Desai, H. Narayanan. vlsid 2007: 863-868 [doi]

2006

Fast DC Analysis and Its Application to Combinatorial Optimization ProblemsGaurav Trivedi, Madhav P. Desai, H. Narayanan. vlsid 2006: 695-700 [doi]

2005

Variance Reduction in Monte Carlo Capacitance ExtractionShabbir H. Batterywala, Madhav P. Desai. vlsid 2005: 85-90 [doi]

On Range Matrices and Wireless Networks in d DimensionsMadhav P. Desai, D. Manjunath. wiopt 2005: 190-196 [doi]

2004

A Novel Technique Towards Eliminating the Global Clock in VLSI CircuitsG. Hazari, Madhav P. Desai, A. Gupta, S. Chakraborty. vlsid 2004: 565-570 [doi]

A Distributed and Pipelined Controller for a Modular and Scalable Hardware EmulatorAditya Mittal, Madhav P. Desai. vlsid 2004: 571 [doi]

On Buffering Schemes for Long Multi-Layer NetsVani Prasad, Madhav P. Desai. vlsid 2004: 455 [doi]

2003

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular functionMadhav P. Desai, H. Narayanan, Sachin B. Patkar. DAM, 131(2):299-310, 2003. [doi]

Detailed Analysis of FIBL in MOS Transistors with High-K Gate DielectricsNihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao. vlsid 2003: 99-104 [doi]

Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer StrategyVani Prasad, Madhav P. Desai. vlsid 2003: 417-422 [doi]

2002

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing LatchesMaryam Shojaei Baghini, Madhav P. Desai. vlsid 2002: 317 [doi]

On the connectivity in finite ad hoc networksMadhav P. Desai, D. Manjunath. icl, 6(10):437-439, 2002. [doi]

2001

2000

Inductance Characterization of Small Interconnects Using Test-Signal MethodJeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal. vlsid 2000: 376 [doi]

1999

A State Assignment Scheme Targeting Performance and AreaB. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai. vlsid 1999: 378-383 [doi]

Decomposition of Finite State Machines for Area, Delay MinimizationRupesh S. Shelar, Madhav P. Desai, H. Narayanan. iccd 1999: 620-625 [doi]

1998

Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS MicroprocessorNevine Nassif, Madhav P. Desai, Dale H. Hall. dac 1998: 230-235 [doi]

1996

A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit SimulationMadhav P. Desai, Yao-Tsung Yen. dac 1996: 125-130 [doi]

Sizing of Clock Distribution Networks for High Performance CPU ChipsMadhav P. Desai, Radenko Cvijetic, James Jensen. dac 1996: 389-394 [doi]

1993

On the Convergence of Reversible Markov ChainsMadhav P. Desai, Vasant B. Rao. siammax, 14(4):950-966, October 1993. [doi]

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