Manfred Glesner - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 100 from 347

2017

VLSI-SoC: An Enduring TraditionRicardo Reis, Manfred Glesner. vlsi 2019: 240-255 [doi]

2014

High-level abstraction for teaching smart systems design with modular hardwareFrançois Philipp, Manfred Glesner. ewme 2014: 146-150 [doi]

2013

Design of an organic electronic label on a flexible substrate for temperature sensingRamkumar Ganesan, Jürgen Krumm, Sebastian Pankalla, Klaus Ludwig, Manfred Glesner. esscirc 2013: 423-426 [doi]

Embedded systems design for smart system integrationManfred Glesner, François Philipp. isvlsi 2013: 32-33 [doi]

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approachLuciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Möller, Leandro Soares Indrusiak, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert, Fernando Moraes. tecs, 12(3):75, 2013. [doi]

An event-based middleware for the remote management of runtime hardware reconfigurationFrançois Philipp, Manfred Glesner. fpl 2013: 1-4 [doi]

Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-ChipFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. tpds, 24(7):1411-1421, 2013. [doi]

2012

Implementation and outcomes of FPGA-based system design in Mongolian educationD. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner. fpl 2012: 491-494 [doi]

Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCsLeandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner. issoc 2012: 1-4 [doi]

Hardware acceleration of combined cipher and forward error correction for low-power wireless applicationsFrançois Philipp, Conrad Klytta, Manfred Glesner, Elvio Dutra. recosoc 2012: 1-7 [doi]

2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable ArchitectureFrançois Philipp, Manfred Glesner. fpl 2012: 679-682 [doi]

Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing methodFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. mam, 36(6):449-461, 2012. [doi]

Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461Faizal Arya Samman, Thomas Hollstein, Manfred Glesner. mam, 36(6):527, 2012. [doi]

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling SchemeÉlvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner. ijrc, 2012, 2012. [doi]

2011

Invited paper: Design criteria for dependable System-on-Chip architecturesThomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann. recosoc 2011: 1-6 [doi]

Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based frameworkLuciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Soares Indrusiak, Leandro Möller, Manfred Glesner, Gilles Sassatelli, Michel Robert, Fernando Moraes. sbcci 2011: 185-190 [doi]

Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor NodeFrançois Philipp, Manfred Glesner. fpl 2011: 396-398 [doi]

A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing UnitFrançois Philipp, Manfred Glesner. ipps 2011: 334-337 [doi]

Design of an autonomous platform for distributed sensing-actuating systemsFrançois Philipp, Faizal Arya Samman, Manfred Glesner. rsp 2011: 85-90 [doi]

On-chip efficient Round-Robin scheduler for high-speed interconnectionSurapong Pongyupinpanich, Manfred Glesner. rsp 2011: 199-202 [doi]

Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDICSurapong Pongyupinpanich, Manfred Glesner. fpl 2011: 382-384 [doi]

Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systemsFaizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner. recosoc 2011: 1-6 [doi]

Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systemsFaizal Arya Samman, François Philipp, Manfred Glesner. asplos 2011: 1-8 [doi]

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chipFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. mam, 35(3):343-358, 2011. [doi]

New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-ChipFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. tpds, 22(4):544-557, 2011. [doi]

RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifierPing Zhao, Manfred Glesner. iscas 2011: 2477-2480 [doi]

2010

Dynamically Reconfigurable Systems for Wireless Sensor NetworksHeiko Hinkelmann, Peter Zipf, Manfred Glesner. In Marco Platzner, Jürgen Teich, Norbert Wehn, editors, Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. pages 315-334, Springer, 2010. [doi]

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip PlatformsSanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes. ijertcs, 1(1):86-101, 2010. [doi]

A case study of hierarchically heterogeneous application modelling using UML and Ptolemy IISanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi. issoc 2010: 68-71 [doi]

Instruction Set Simulator for MPSoCs based on NoCs and MIPS ProcessorsLeandro Möller, André Rodrigues, Fernando Moraes 0001, Leandro Soares Indrusiak, Manfred Glesner. recosoc 2010: 7-11

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of RoutersLeandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner. fpl 2010: 229-233 [doi]

Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-ChipFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. tvlsi, 18(7):1067-1080, 2010. [doi]

Novel method of chaotic systems evaluation for implementations of encryption algorithmsÉlvio Dutra, Manfred Glesner, Weiler Alves Finamore, Leandro Soares Indrusiak. ICT 2010: 89-96 [doi]

2009

Providing Memory Management Abstraction for Self-Reconfigurable Video Processing PlatformsKurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner. ijrc, 2009, 2009. [doi]

A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect StructuresPetru Bogdan Bacinschi, Manfred Glesner. vlsi 2011: 156-180 [doi]

Generation of Synthetic Floating-Point benchmark circuitsT. Chun Pong Chau, S. Man Ho Ho, Philip H. W. Leong, Peter Zipf, Manfred Glesner. ipps 2009: 1-9 [doi]

A flexible floating-point wavelet transform and wavelet packet processorAndre Guntoro, Manfred Glesner. date 2009: 1314-1319 [doi]

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodesHeiko Hinkelmann, Peter Zipf, Manfred Glesner. fpl 2009: 359-366 [doi]

On the design of reconfigurable multipliers for integer and Galois field multiplicationHeiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner. mam, 33(1):2-12, 2009. [doi]

Characterising embedded applications using a UML profileSanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi. issoc 2009: 172-175 [doi]

Low-Power Coding for Networks-on-Chip with Virtual ChannelsAlberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner. jolpe, 5(1):77-84, 2009. [doi]

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAsMarkus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. fpl 2009: 92-98 [doi]

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping ManagementFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. vlsi, 2009, 2009. [doi]

Towards a unique FPGA-based identification circuit using process variationsHaile Yu, Philip H. W. Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf. fpl 2009: 397-402 [doi]

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-ChipsPeter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner. ijrc, 2009, 2009. [doi]

2008

Enabling self-reconfiguration on a video processing platformKurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner. sies 2008: 19-26 [doi]

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor PairsPetru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner. date 2008: 698-703 [doi]

A fast and compact classifier based on sorting in an iteratively expanded input spaceRadu Dogaru, Manfred Glesner. ijis, 23(5):607-618, 2008. [doi]

Coarse-grained reconfigurationSven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. fpl 2008: 349 [doi]

Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet ProcessorAndre Guntoro, Hans-Peter Keil, Manfred Glesner. sigmap 2008: 69-75

A lifting-based DWT and IDWT processor with multi-context configuration and normalization factorAndre Guntoro, Manfred Glesner. fpl 2008: 479-482 [doi]

Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filtersAndre Guntoro, Manfred Glesner. asap 2008: 299-304 [doi]

Low-latency VLSI architecture of a 3-input floating-point adderAndre Guntoro, Manfred Glesner. apccas 2008: 180-183 [doi]

High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transformsAndre Guntoro, Massoud Momeni, Hans-Peter Keil, Manfred Glesner. apccas 2008: 457-460 [doi]

A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet FiltersAndre Guntoro, Manfred Glesner. vlsi 2010: 154-173 [doi]

High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet ProcessorAndre Guntoro, Hans-Peter Keil, Manfred Glesner. icete 2009: 318-330 [doi]

High-performance fpga-based floating-point adder with three inputsAndre Guntoro, Manfred Glesner. fpl 2008: 627-630 [doi]

A Flexible Floating-Point Wavelet ProcessorAndre Guntoro, Manfred Glesner. sitis 2008: 403-410 [doi]

A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging SupportHeiko Hinkelmann, Andreas Reinhardt, Manfred Glesner. rsp 2008: 82-88 [doi]

A scalable reconfiguration mechanism for fast dynamic reconfigurationHeiko Hinkelmann, Peter Zipf, Manfred Glesner. fpt 2008: 145-152 [doi]

Application-specific reconfigurable processorsHeiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll. fpl 2008: 350 [doi]

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip InterconnectsLeandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner. isvlsi 2008: 491-494 [doi]

A novel leakage-estimation method for input-vector controlHans-Peter Keil, Massoud Momeni, Andre Guntoro, Alberto García Ortiz, Manfred Glesner. apccas 2008: 570-573 [doi]

Comparison of Opamp-Based and Comparator-Based Delta-Sigma ModulationMassoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner. date 2008: 688-693 [doi]

Impact of circuit nonidealities on the implementation of switched-capacitor resonatorsMassoud Momeni, Andre Guntoro, Hans-Peter Keil, Manfred Glesner. apccas 2008: 1624-1627 [doi]

Validation of executable application models mapped onto network-on-chip platformsSanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes. sies 2008: 118-125 [doi]

An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor NetworksEnkhbold Ochirsuren, Leandro Soares Indrusiak, Manfred Glesner. icdcsw 2008: 174-179 [doi]

TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable ProcessorEnkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner. ifip10-3 2008: 161-170 [doi]

PMD: A Low-Power Code for Networks-on-Chip Based on Virtual ChannelsAlberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner. patmos 2009: 219-228 [doi]

A simplified executable model to evaluate latency and throughput of networks-on-chipLuciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi. sbcci 2008: 170-175 [doi]

Process variations aware robust on-chip bus architecture synthesis for MPSoCsSujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner. iscas 2008: 2989-2992 [doi]

Flexible parallel pipeline network-on-chip based on dynamic packet identity managementFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. ipps 2008: 1-8 [doi]

Multicast Parallel Pipeline Router Architecture for Network-on-ChipFaizal Arya Samman, Thomas Hollstein, Manfred Glesner. date 2008: 1396-1401 [doi]

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy IIChristopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil. rsp 2008: 196-202 [doi]

An area-efficient FPGA realisation of a codebook-based image compression methodPeter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner. fpt 2008: 349-352 [doi]

2007

System Level Design of a Dynamically Self-Reconfigurable Image Processing SystemKurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner. recosoc 2007: 47-54

On the Design of a Reconfigurable Multiplier for Integer and Galois Field MultiplicationHeiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner. recosoc 2007: 185-191

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor NetworksHeiko Hinkelmann, Peter Zipf, Manfred Glesner. fpt 2007: 313-316 [doi]

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme)Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck. it, 49(3):174, 2007. [doi]

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platformsThomas Hollstein, Manfred Glesner. cee, 33(4):310-319, 2007. [doi]

Specification of alternative execution semantics of UML sequence diagrams within actor-oriented modelsLeandro Soares Indrusiak, Manfred Glesner. sbcci 2007: 330-335 [doi]

Interactive presentation: Executable system-level specification models containing UML-based behavioral patternsLeandro Soares Indrusiak, Andreas Thuy, Manfred Glesner. date 2007: 301-306 [doi]

On the Evolution of Remote Laboratories for Prototyping Digital Electronic SystemsLeandro Soares Indrusiak, Manfred Glesner, Ricardo Reis. tie, 54(6):3069-3077, 2007. [doi]

On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron InterconnectsTudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner. patmos 2007: 242-254 [doi]

Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive CouplingTudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner. recosoc 2007: 7-14

Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear SystemsAlberto García Ortiz, Tudor Murgan, Manfred Glesner. jolpe, 3(2):189-198, 2007. [doi]

Reducing the Power Consumption in Networks-on-Chip through Data Coding SchemesJosé Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Ricardo Reis, Manfred Glesner. icecsys 2007: 1007-1010 [doi]

Inserting Data Encoding Techniques into NoC-Based SystemsJosé Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis. isvlsi 2007: 299-304 [doi]

Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data TrafficSujan Pandey, Manfred Glesner. tvlsi, 15(10):1111-1124, 2007. [doi]

An Efficient Fractional-Rate Interpolation ArchitectureMihail Petrov, Manfred Glesner. globecom 2007: 4554-4558 [doi]

A Scalable Resampling ArchitectureMihail Petrov, Manfred Glesner. globecom 2007: 3102-3106 [doi]

Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer HardwarestrukturenPeter Zipf, Yang Qiao, Manfred Glesner. mbmv 2007: 253-262

A Customizable LEON2-Based VLIW ProcessorPeter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner. recosoc 2007: 55-60

A Power Estimation Model for an FPGA-based Softcore ProcessorPeter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll. fpl 2007: 171-176 [doi]

2006

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and RepeatersTudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner. vlsi 2006: 302-307 [doi]

Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based ArchitectureSujan Pandey, Nurten Utlu, Manfred Glesner. vlsi 2006: 222-227 [doi]

Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable ArchitectureSujan Pandey, Manfred Glesner. fpl 2006: 1-6 [doi]

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraintSujan Pandey, Manfred Glesner. dac 2006: 663-668 [doi]

Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling techniqueSujan Pandey, Manfred Glesner. iscas 2006: [doi]

A CMOS Compatible Charge Recovery Logic Family for Low Supply VoltagesClemens Schlachta, Manfred Glesner. patmos 2006: 563-572 [doi]

All Publications

Filter by Year

[-]
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag

[+]
OR AND NOT 1

Filter by Venue

[+]
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1

Researchr

Publications by 'Manfred Glesner'

Viewing Publication 1 - 100 from 347

2017

2014

2013

2012

2011

2010

2009

2008

2007

2006

All Publications

Filter by Year [-]OR AND NOT 1

Filter by TypeOR AND NOT 1

Filter by Tag [+]OR AND NOT 1

Filter by Venue [+]OR AND NOT 1

Filter by Author [+]OR AND NOT 1

Filter by Top Terms [+]OR AND NOT 1

Researchr

Publications by 'Manfred Glesner'

Viewing Publication 1 - 100 from 347

2017

2014

2013

2012

2011

2010

2009

2008

2007

2006

Filter by Year

[-]
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag

[+]
OR AND NOT 1

Filter by Venue

[+]
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1