Mary Jane Irwin - researchr alias

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2011

2010

Dynamic core partitioning for energy efficiencyYang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan. ipps 2010: 1-8 [doi]

Total Power Optimization for Combinational Logic Using Genetic AlgorithmsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. vlsisp, 58(2):145-160, 2010. [doi]

Technology scaling redirects main memories: technical perspectiveMary Jane Irwin. CACM, 53(7):98, 2010. [doi]

Shared caches in multicores: the good, the bad, and the uglyMary Jane Irwin. isca 2010: 234 [doi]

Cache topology aware computation mapping for multicoresMahmut T. Kandemir, Taylan Yemliha, Sai Prashanth Muralidhara, Shekhar Srikantaiah, Mary Jane Irwin, Yuanrui Zhang. PLDI 2010: 74-85 [doi]

T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPsKonrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin. ipps 2010: 1-8 [doi]

On the Effects of Process Variation in Network-on-Chip ArchitecturesChrysostomos Nicopoulos, Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary Jane Irwin. tdsc, 7(3):240-254, 2010. [doi]

On-chip memory space partitioning for chip multiprocessors using polyhedral algebraOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. iet-cdt, 4(6):484-498, 2010. [doi]

Compiler directed network-on-chip reliability enhancement for chip multiprocessorsOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan. lctrts 2010: 85-94 [doi]

Optimizing power and performance for reliable on-chip networksAditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan. aspdac 2010: 431-436 [doi]

2009

Adapting application execution in CMPs using helper threadsYang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin. jpdc, 69(9):790-806, 2009. [doi]

Adapting Application Mapping to Systematic Within-Die Process Variations on Chip MultiprocessorsYang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan. hipeac 2009: 231-247 [doi]

Compiler-assisted soft error detection under performance and energy constraints in embedded systemsJie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. tecs, 8(4), 2009. [doi]

Process-Variation-Aware Adaptive Cache Architecture and ManagementMadhu Mutyam, Feng Wang 0004, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. TC, 58(7):865-877, 2009. [doi]

Arithmetic unit design using 180nm TSV-based 3D stacking technologyJin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin. 3dic 2009: 1-4 [doi]

Using Data Compression for Increasing Memory System UtilizationOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. tcad, 28(6):901-914, 2009. [doi]

Modeling Soft Errors at the Device and Logic Levels for Combinational CircuitsRajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu. tdsc, 6(3):202-216, 2009. [doi]

Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009Mary Lou Soffa, Mary Jane Irwin, editors, ACM, 2009.

In-Network Caching for Chip MultiprocessorsAditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan. hipeac 2009: 373-388 [doi]

2008

Ring data location prediction scheme for Non-Uniform Cache ArchitecturesSayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin. iccd 2008: 693-698 [doi]

A helper thread based EDP reduction scheme for adapting application execution in CMPsYang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin. ipps 2008: 1-14 [doi]

A novel migration-based NUCA design for chip multiprocessorsMahmut T. Kandemir, Feihui Li, Mary Jane Irwin, Seung Woo Son. sc 2008: 28 [doi]

Implementation and evaluation of a migration-based NUCA design for chip multiprocessorsFeihui Li, Mahmut T. Kandemir, Mary Jane Irwin. sigmetrics 2008: 449-450 [doi]

A low-power phase change memory based hybrid cache architecturePrasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim. glvlsi 2008: 395-398 [doi]

Managing power, performance and reliability trade-offsPadma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin, Konrad Malkowski. ipps 2008: 1-5 [doi]

Hierarchical Soft Error Estimation Tool (HSEET)Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu. isqed 2008: 680-683 [doi]

Analysis and solutions to issue queue process variationNiranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. dsn 2008: 11-21 [doi]

Adaptive set pinning: managing shared caches in chip multiprocessorsShekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin. asplos 2008: 135-144 [doi]

Toward Increasing FPGA LifetimeSuresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari. tdsc, 5(2):115-127, 2008. [doi]

Design Space Exploration for 3-D CacheYuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. tvlsi, 16(4):444-455, 2008. [doi]

Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computationsAditya Yanamandra, Bryan Cover, Padma Raghavan, Mary Jane Irwin, Mahmut T. Kandemir. ipps 2008: 1-10 [doi]

Integrated code and data placement in two-dimensional mesh based chip multiprocessorsTaylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin. iccad 2008: 583-588 [doi]

2007

On-chip bus thermal analysis and optimisationFeng Wang 0004, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. iet-cdt, 1(5):590-599, 2007. [doi]

Ring Prediction for Non-Uniform Cache ArchitecturesSayaka Akioka, Feihui Li, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin. IEEEpact 2007: 401 [doi]

Evolving the ACM journal distribution programRonald F. Boisvert, Mary Jane Irwin, Holly E. Rushmeier. CACM, 50(9):19-20, 2007. [doi]

Link Shutdown Opportunities During Collective Communications in 3-D Torus NetsS. Conner, Sayaka Akioka, Mary Jane Irwin, Padma Raghavan. ipps 2007: 1-8 [doi]

Optimising power efficiency in trace cache fetch unitJie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. iet-cdt, 1(4):334-348, 2007. [doi]

Reducing non-deterministic loads in low-power caches via early cache set resolutionSoontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin. mam, 31(5):293-301, 2007. [doi]

Load Miss Prediction - Exploiting Power Performance Trade-offsKonrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin. ipps 2007: 1-8 [doi]

Memory Optimizations For Fast Power-Aware Sparse ComputationsKonrad Malkowski, Padma Raghavan, Mary Jane Irwin. ipps 2007: 1-6 [doi]

Phase-aware adaptive hardware selection for power-efficient scientific computationsKonrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin. islped 2007: 403-406 [doi]

Variation Analysis of CAM CellsAmol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. isqed 2007: 333-338 [doi]

Variation Impact on SER of Combinational CircuitsKrishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. isqed 2007: 911-916 [doi]

Impact of NBTI on FPGAsKrishnan Ramakrishnan, S. Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2007: 717-722 [doi]

Investigating Simple Low Latency Reliable Multiported Register FilesAndrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin. isvlsi 2007: 375-382 [doi]

Architecting Microprocessor Components in 3D Design SpaceBalaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2007: 103-108 [doi]

Reliability-aware Co-synthesis for Embedded SystemsYuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsisp, 49(1):87-99, 2007. [doi]

2006

Reducing dynamic and leakage energy in VLIW architecturesWei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. tecs, 5(1):1-28, 2006. [doi]

On-chip bus thermal analysis and optimizationFeng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. date 2006: 850-855 [doi]

Characterizing the Performance and Energy Attributes of Scientific SimulationsSayaka Akioka, Konrad Malkowski, Padma Raghavan, Mary Jane Irwin, Lois C. McInnes, Boyana Norris. iccS 2006: 242-249 [doi]

Plagiarism on the riseRonald F. Boisvert, Mary Jane Irwin. CACM, 49(6):23-24, 2006. [doi]

Reducing code size through address register assignmentGuilin Chen, Mahmut T. Kandemir, Mary Jane Irwin, J. Ramanujam. tecs, 5(1):225-258, 2006. [doi]

Reducing NoC energy consumption through compiler-directed channel voltage scalingGuangyu Chen, Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin. PLDI 2006: 193-203 [doi]

Object duplication for improving reliabilityGuilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. aspdac 2006: 140-145 [doi]

Poster reception - Energy/performance modeling for collective communication in 3-D torus cluster networksS. Conner, Greg M. Link, S. Tobita, Mary Jane Irwin, Padma Raghavan. sc 2006: 138 [doi]

Interconnect and Thermal-aware Floorplanning for 3D MicroprocessorsWei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. isqed 2006: 98-104 [doi]

Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 06), Ottawa, Ontario, Canada, June 14-16, 2006Mary Jane Irwin, Koen De Bosschere, editors, ACM, 2006.

Activity clustering for leakage management in SPMsMahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu. date 2006: 696-697 [doi]

Block-based frequency scalable technique for efficient hierarchical codingJooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli. tsp, 54(7):2559-2566, 2006. [doi]

An efficient architecture for motion estimation and compensation in the transform domainJooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. tcsv, 16(2):191-201, 2006. [doi]

Inverse discrete cosine transform architecture exploiting sparseness and symmetry propertiesJooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin. tcsv, 16(5):655-662, 2006. [doi]

Enhancing L2 organization for CMPs with a center cellChun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin. ipps 2006: [doi]

On improving performance and energy profiles of sparse scientific applicationsKonrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin. ipps 2006: [doi]

Conjugate gradient sparse solvers: performance-power characteristicsKonrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin. ipps 2006: [doi]

Poster reception - Toward a power efficient computer architecture for Barnes-Hut N-body simulationsKonrad Malkowski, Padma Raghavan, Mary Jane Irwin. sc 2006: 146 [doi]

Compiler-directed thermal management for VLIW functional unitsMadhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. lctrts 2006: 163-172 [doi]

Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip MultiprocessorsOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun. icpads 2006: 383-390 [doi]

SEAT-LA: A Soft Error Analysis Tool for Combinational LogicR. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. vlsid 2006: 499-502 [doi]

Priority scheduling in digital microfluidics-based biochipsAndrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin. date 2006: 329-334 [doi]

A Parallel Architecture for Hardware Face DetectionTheo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin. isvlsi 2006: 452-453 [doi]

2005

Exploiting frequent field values in java objects for reducing heap memory requirementsGuangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin. vee 2005: 68-78 [doi]

Compiler-directed selective data protection against soft errorsG. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik. aspdac 2005: 713-716 [doi]

Soft errors issues in low-power cachesVijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. tvlsi, 13(10):1157-1166, 2005. [doi]

Exploring technology alternatives for nano-scale FPGA interconnectsAman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin. dac 2005: 921-926 [doi]

Compiler-Directed Instruction Duplication for Soft Error DetectionJie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. date 2005: 1056-1057 [doi]

Thermal-Aware Task Allocation and Scheduling for Embedded SystemsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. date 2005: 898-899 [doi]

Thermal-Aware Floorplanning Using Genetic AlgorithmsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin. isqed 2005: 634-639 [doi]

A Nanosensor Array-Based VLSI Gas DiscriminatorKevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2005: 241-246 [doi]

EditorialMary Jane Irwin, Narayanan Vijaykrishnan. jetc, 1(1):1-6, 2005. [doi]

Compiler-directed high-level energy estimation and optimizationIsmail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam. tecs, 4(4):819-850, 2005. [doi]

An integer linear programming-based tool for wireless sensor networksIsmail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. jpdc, 65(3):247-260, 2005. [doi]

Compiler-guided leakage optimization for banked scratch-pad memoriesMahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu. tvlsi, 13(10):1136-1146, 2005. [doi]

High Performance Array Processor for Video DecodingJ. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin. isvlsi 2005: 28-33 [doi]

Compiler-directed proactive power management for networksFeihui Li, Guangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin. cases 2005: 137-146 [doi]

Exploiting Barriers to Optimize Power Consumption of CMPsChun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin. ipps 2005: [doi]

Analysis of Error Recovery Schemes for Networks on ChipsSrinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli. dt, 22(5):434-442, 2005. [doi]

Increasing on-chip memory space utilization for embedded chip multiprocessors through data compressionOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. codes 2005: 87-92 [doi]

Customized on-chip memories for embedded chip multiprocessorsOzcan Ozturk, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy. aspdac 2005: 743-748 [doi]

BB-GC: Basic-Block Level Garbage CollectionOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. date 2005: 1032-1037 [doi]

Symmetric encryption in reconfigurable and custom hardwareEric J. Swankoski, Narayanan Vijaykrishnan, Richard R. Brooks, Mahmut T. Kandemir, Mary Jane Irwin. ijes, 1(3/4):205-217, 2005. [doi]

Networks on Chip (NoC): Interconnects of Next Generation Systems on ChipTheocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin. ac, 63:36-92, 2005.

Implementing LDPC Decoding on Network-on-ChipTheo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2005: 134-137 [doi]

Influence of Leakage Reduction Techniques on Delay/Leakage UncertaintyYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. vlsid 2005: 374-379 [doi]

Leakage-Aware Interconnect for On-Chip NetworkYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. date 2005: 230-231 [doi]

Three-Dimensional Cache Design Exploration Using 3DCactiYuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. iccd 2005: 519-524 [doi]

Designing reliable circuit in the presence of soft errorsNarayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. aspdac 2005: 1 [doi]

Optimizing sensor movement planning for energy efficiencyGuiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Thomas F. La Porta. islped 2005: 215-220 [doi]

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