Mateo Valero - researchr alias

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2011

RVC: a mechanism for time-analyzable real-time processors with faulty cachesJaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero. hipeac 2011: 97-106 [doi]

RVC-based time-predictable faulty caches for safety-critical systemsJaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides. iolts 2011: 25-30 [doi]

Assessing Accelerator-Based HPC Reverse Time MigrationMauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, Mateo Valero. tpds, 22(1):147-162, 2011. [doi]

The International Exascale Software Project roadmapJack Dongarra, Peter H. Beckman, Terry Moore, Patrick Aerts, Giovanni Aloisio, Jean-Claude Andre, David Barkai, Jean-Yves Berthou, Taisuke Boku, Bertrand Braunschweig, Franck Cappello, Barbara M. Chapman, Xuebin Chi, Alok N. Choudhary, Sudip S. Dosanjh, Thom H. Dunning, Sandro Fiore, Al Geist, Bill Gropp, Robert J. Harrison, Mark Hereld, Michael A. Heroux, Adolfy Hoisie, Koh Hotta, Zhong Jin, Yutaka Ishikawa, Fred Johnson, Sanjay Kale, Richard Kenway, David E. Keyes, Bill Kramer, Jesús Labarta, Alain Lichnewsky, Thomas Lippert, Bob Lucas, Barney Maccabe, Satoshi Matsuoka, Paul Messina, Peter Michielse, Bernd Mohr, Matthias S. Müller, Wolfgang E. Nagel, Hiroshi Nakashima, Michael E. Papka, Daniel A. Reed, Mitsuhisa Sato, Edward Seidel, John Shalf, David Skinner, Marc Snir, Thomas L. Sterling, Rick Stevens, Fred Streitz, Bob Sugar, Shinji Sumimoto, William Tang, John Taylor, Rajeev Thakur, Anne E. Trefethen, Mateo Valero, Aad van der Steen, Jeffrey S. Vetter, Peg Williams, Robert Wisniewski, Katherine A. Yelick. ijhpca, 25(1):3-60, 2011. [doi]

Simulating Whole Supercomputer ApplicationsJuan Gonzalez, Judit Gimenez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero. micro, 31(3):32-45, 2011. [doi]

Energy-Aware Accounting and Billing in Large-Scale Computing FacilitiesVictor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero. micro, 31(3):60-71, 2011. [doi]

RMS-TM: a comprehensive benchmark suite for transactional memory systemsGokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero. wosp 2011: 335-346 [doi]

Hybrid high-performance low-power and ultra-low energy reliable cachesBojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero. cf 2011: 12 [doi]

Dynamic Cache Partitioning Based on the MLP of Cache MissesMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. thipeac, 3:3-23, 2011. [doi]

IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time SystemsMarco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Robert I. Davis, Mateo Valero. rtas 2011: 280-290 [doi]

Trace-driven simulation of multithreaded applicationsAlejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero. ispass 2011: 87-96 [doi]

Circuit design of a dual-versioning L1 data cache for optimistic concurrencyAzam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. glvlsi 2011: 325-330 [doi]

The Impact of Application s Micro-Imbalance on the Communication-Computation OverlapVladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero. pdp 2011: 191-198 [doi]

Quantifying the Potential Task-Based Dataflow Parallelism in MPI ApplicationsVladimir Subotic, Roger Ferrer, José Carlos Sancho, Jesús Labarta, Mateo Valero. europar 2011: 39-51 [doi]

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory SystemNehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero. fccm 2011: 146-153 [doi]

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore PrototypeNehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero. arc 2011: 350-362 [doi]

Hybrid Transactional Memory with Pessimistic Concurrency ControlEnrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman S. Unsal, Adrián Cristal, Mateo Valero. ijpp, 39(3):375-396, 2011. [doi]

An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded ArchitecturesRuken Zilan, Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero. mascots 2011: 478-481 [doi]

2010

On the Problem of Evaluating the Performance of Multiprogrammed WorkloadsFrancisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero. TC, 59(12):1722-1728, 2010. [doi]

BSLD threshold driven power management policy for HPC centersMaja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero. ipps 2010: 1-8 [doi]

Utilization driven power-aware parallel job schedulingMaja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero. ife, 25(3-4):207-216, 2010. [doi]

Optimizing job performance under a given power constraint in HPC centersMaja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero. green 2010: 257-267 [doi]

Task Superscalar: An Out-of-Order Task PipelineYoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero. micro 2010: 89-100 [doi]

Designing OS for HPC Applications: SchedulingRoberto Gioiosa, Sally A. McKee, Mateo Valero. cluster 2010: 78-87 [doi]

Scalability Analysis of Progressive Alignment on a MulticoreSebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero. cisis 2010: 889-894 [doi]

Trends and techniques for energy efficient architecturesVictor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero. vlsi 2010: 276-279 [doi]

Power and thermal characterization of POWER6 systemVictor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose. IEEEpact 2010: 7-18 [doi]

Exploiting Inactive Rename Slots for Detecting Soft ErrorsMehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero. arcs 2010: 126-137 [doi]

Adapting cache partitioning algorithms to pseudo-LRU replacement policiesKamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero. ipps 2010: 1-12 [doi]

Effective communication and computation overlap with hybrid MPI/SMPSsVladimir Marjanovic, JesÃºs Labarta, Eduard AyguadÃ©, Mateo Valero. ppopp 2010: 337-338 [doi]

Overlapping communication and computation by using a hybrid MPI/SMPSs approachVladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero. ics 2010: 5-16 [doi]

Load balancing using dynamic cache allocationMiquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero. cf 2010: 153-164 [doi]

Thread to strand binding of parallel network applications in massive multi-threaded systemsPetar Radojkovic, Vladimir Cakarevic, Javier VerdÃº, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero. ppopp 2010: 191-202 [doi]

Efficient runahead threadsTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero. IEEEpact 2010: 443-452 [doi]

A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific ApplicationsVladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero. cluster 2010: 275-283 [doi]

Simulation environment for studying overlap of communication and computationVladimir Subotic, Jesús Labarta, Mateo Valero. ispass 2010: 115-116 [doi]

Long DNA Sequence Comparison on Multicore ArchitecturesFriman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero. europar 2010: 247-259 [doi]

Multicore: The View from EuropeMateo Valero, Nacho Navarro. micro, 30(5):2-4, 2010. [doi]

Architectural Support for Fair Reader-Writer LockingEnrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero. micro 2010: 275-286 [doi]

Discovering and understanding performance bottlenecks in transactional applicationsFerad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero. IEEEpact 2010: 285-294 [doi]

Debugging programs that use atomic blocks and transactional memoryFerad Zyulkyarov, Tim Harris, Osman S. Unsal, AdriÃ¡n Cristal, Mateo Valero. ppopp 2010: 57-66 [doi]

2009

Thread to Core Assignment in SMT On-Chip MultiprocessorsCarmelo Acosta, Francisco J. Cazorla, Alex RamÃrez, Mateo Valero. sbac-pad 2009: 67-74 [doi]

Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMAMauricio Alvarez, Alex Ramírez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck. rasi, 6(1):219-228, 2009. [doi]

Characterizing the resource-sharing levels in the UltraSPARC T2 processorVladimir Cakarevic, Petar Radojkovic, Javier VerdÃº, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero. micro 2009: 481-492 [doi]

The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance CommunityJack Dongarra, Pete Beckman, Patrick Aerts, Franck Cappello, Thomas Lippert, Satoshi Matsuoka, Paul Messina, Terry Moore, Rick Stevens, Anne E. Trefethen, Mateo Valero. ijhpca, 23(4):309-322, 2009. [doi]

Power-aware load balancing of large scale MPI applicationsMaja Etinski, Julita CorbalÃ¡n, JesÃºs Labarta, Mateo Valero, Alexander V. Veidenbaum. ipps 2009: 1-8 [doi]

QuakeTM: parallelizing a complex sequential application using transactional memoryVladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero. ics 2009: 126-135 [doi]

Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactionsChinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. ppopp 2009: 307-308 [doi]

BSC Vision Towards ExascaleJesÃºs Labarta, Eduard AyguadÃ©, Mateo Valero. ijhpca, 23(4):340-343, 2009. [doi]

CPU Accounting in CMP ProcessorsCarlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. cal, 8(1):17-20, 2009. [doi]

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPsCarlos Luque, Miquel MoretÃ³, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero. IEEEpact 2009: 203-213 [doi]

Scalability of Macroblock-level Parallelism for H.264 DecodingM. Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero. icpads 2009: 236-243 [doi]

FlexDCP: a QoS framework for CMP architecturesMiquel MoretÃ³, Francisco J. Cazorla, Alex RamÃrez, Rizos Sakellariou, Mateo Valero. sigops, 43(2):86-96, 2009. [doi]

Hardware support for WCET analysis of hard real-time multicore systemsMarco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero. isca 2009: 57-68 [doi]

Code Semantic-Aware Runahead ThreadsTanausÃº RamÃrez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. icpp 2009: 437-444 [doi]

Available task-level parallelism on the Cell BEAlejandro Rico, Alex RamÃrez, Mateo Valero. sp, 17(1-2):59-76, 2009. [doi]

Oblivious routing schemes in extended generalized Fat Tree networksGermÃ¡n RodrÃguez, Cyriel Minkenberg, RamÃ³n Beivide, Ronald P. Luijten, JesÃºs Labarta, Mateo Valero. cluster 2009: 1-8 [doi]

Exploring pattern-aware routing in generalized fat tree networksGermán Rodríguez, Ramón Beivide, Cyriel Minkenberg, Jesús Labarta, Mateo Valero. ics 2009: 276-285 [doi]

DIA: A Complexity-Effective Decoding ArchitectureOliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero. TC, 58(4):448-462, 2009. [doi]

Clock gate on abort: Towards energy-efficient hardware Transactional MemorySutirtha Sanyal, Sourav Roy, AdriÃ¡n Cristal, Osman S. Unsal, Mateo Valero. ipps 2009: 1-8 [doi]

Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional MemorySutirtha Sanyal, Sourav Roy, AdriÃ¡n Cristal, Osman S. Unsal, Mateo Valero. hpcc 2009: 171-179 [doi]

Quantitative analysis of sequence alignment applications on multiprocessor architecturesFriman Sánchez, Alex Ramírez, Mateo Valero. cf 2009: 61-70 [doi]

Taking the heat off transactions: Dynamic selection of pessimistic concurrency controlNehir SÃ¶nmez, Tim Harris, AdriÃ¡n Cristal, Osman S. Unsal, Mateo Valero. ipps 2009: 1-10 [doi]

EazyHTM: eager-lazy hardware transactional memorySasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, AdriÃ Armejach, AdriÃ¡n Cristal, Osman S. Unsal, Tim Harris, Mateo Valero. micro 2009: 145-155 [doi]

A european perspective on supercomputingMateo Valero. ics 2009: 1 [doi]

Atomic quake: using transactional memory in an interactive multiplayer game serverFerad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero. ppopp 2009: 25-34 [doi]

2008

MFLUSH: Handling Long-Latency Loads in SMT On-Chip MultiprocessorsCarmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. icpp 2008: 173-181 [doi]

Selection of the Register File Size and the Resource Allocation Policy on SMT ProcessorsJesÃºs Alastruey, Teresa Monreal, Francisco J. Cazorla, VÃctor ViÃ±als, Mateo Valero. sbac-pad 2008: 63-70 [doi]

A dynamic scheduler for balancing HPC applicationsCarlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero. sc 2008: 41 [doi]

Balancing HPC applications through smart allocation of resources in MT processorsCarlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero. ipps 2008: 1-12 [doi]

Software-Controlled Priority Characterization of POWER5 ProcessorCarlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero. isca 2008: 415-426 [doi]

Soft Real-Time Scheduling on SMT Processors with Explicit Resource AllocationCarlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero. arcs 2008: 173-187 [doi]

Architecture Performance Prediction Using Evolutionary Artificial Neural NetworksPedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luís Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee. evoW 2008: 175-183 [doi]

LPA: A First Approach to the Loop Processor ArchitectureAlejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero. hipeac 2008: 273-287 [doi]

A distributed processor state management architecture for large-window processorsIsidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero. euromicro 2008: 11-22 [doi]

Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment ApplicationsSebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero. samos 2008: 53-64 [doi]

Nebelung: Execution Environment for Transactional OpenMPMilos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. ijpp, 36(3):326-346, 2008. [doi]

MLP-Aware Dynamic Cache PartitioningMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. hipeac 2008: 337-352 [doi]

Multicore Resource ManagementKyle J. Nesbit, Miquel MoretÃ³, Francisco J. Cazorla, Alex RamÃrez, Mateo Valero, James E. Smith. micro, 28(3):6-16, 2008. [doi]

The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environmentCristian Perfumo, Nehir Sönmez, Srdjan Stipic, Osman S. Unsal, Adrián Cristal, Tim Harris, Mateo Valero. cf 2008: 67-78 [doi]

A Two-Level Load/Store Queue Based on Execution LocalityMiquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruden González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero. isca 2008: 25-36 [doi]

Vectorized AES Core for High-throughput Secure EnvironmentsMiquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero. vecpar 2008: 83-94 [doi]

Power-efficient VLIW design using clustering and wideningMiquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero. ijes, 3(3):141-149, 2008. [doi]

Measuring Operating System Overhead on CMT ProcessorsPetar Radojkovic, Vladimir Cakarevic, Javier VerdÃº, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero. sbac-pad 2008: 133-140 [doi]

Runahead Threads to improve SMT performanceTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. hpca 2008: 149-158 [doi]

Evolutionary system for prediction and optimization of hardware architecture performancePedro A. Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Sally A. McKee. cec 2008: 1941-1948 [doi]

Supercomputing for the Future, Supercomputing from the Past (Keynote)Mateo Valero, Jesús Labarta. hipeac 2008: 3-5 [doi]

MultiLayer processing - an execution model for parallel stateful packet processingJavier Verdú, Mario Nemirovsky, Mateo Valero. ancs 2008: 79-88 [doi]

2007

Microarchitectural Support for Speculative Register RenamingJesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero. ipps 2007: 1-10 [doi]

Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec ApplicationsMauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero. ispass 2007: 62-71 [doi]

On the Problem of Minimizing Workload Execution Time in SMT ProcessorsFrancisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero. samos 2007: 66-73 [doi]

Implicit Transactional Memory in Kilo-Instruction MultiprocessorsMarco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero. APCSAC 2007: 339-353 [doi]

Transactional Memory: An OverviewTim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero. micro, 27(3):8-29, 2007. [doi]

Transactional Memory and OpenMPMilos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero. iwomp 2008: 37-53 [doi]

Online Prediction of Applications Cache UtilityMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. samos 2007: 169-177 [doi]

MLP-Aware Dynamic Cache PartitioningMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. IEEEpact 2007: 418 [doi]

Runahead Threads: Reducing Resource Contention in SMT ProcessorsTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. IEEEpact 2007: 423 [doi]

Energy saving through a simple load control mechanismTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. sigarch, 35(4):29-36, 2007. [doi]

Enlarging Instruction StreamsOliverio J. Santana, Alex Ramírez, Mateo Valero. TC, 56(10):1342-1357, 2007. [doi]

Hardware Transactional Memory with Operating System Support, HTMOSSasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero. europar 2008: 8-17 [doi]

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