Ming-Dou Ker - researchr alias

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2011

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS processChun-Yu Lin, Li-Wei Chu, Ming-Dou Ker. mr, 51(8):1315-1324, 2011. [doi]

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS processYi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker. mr, 51(5):871-878, 2011. [doi]

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on eventsChih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker. iscas 2011: 1403-1406 [doi]

2010

2009

2008

2007

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuitsShih-Hung Chen, Ming-Dou Ker. mr, 47(9-11):1502-1505, 2007. [doi]

Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS TechnologyMing-Dou Ker, Hung-Tai Liao. iscas 2007: 1121-1124 [doi]

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]

2006

Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage applicationZi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker. iscas 2006: [doi]

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technologyShih-Hung Chen, Ming-Dou Ker. mr, 46(7):1042-1049, 2006. [doi]

ESD robustness of thin-film devices with different layout structures in LTPS technologyChih-Kang Deng, Ming-Dou Ker. mr, 46(12):2067-2073, 2006. [doi]

Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking MaskHsin-Chyh Hsu, Ming-Dou Ker. isqed 2006: 503-506 [doi]

New matching methodology of low-noise amplifier with ESD protectionBo-Shih Huang, Ming-Dou Ker. iscas 2006: [doi]

Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applicationsMing-Dou Ker, Chien-Hua Wu. iscas 2006: [doi]

Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS TechnologyTai-Xiang Lai, Ming-Dou Ker. isqed 2006: 597-602 [doi]

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system boardKun-Hsien Lin, Ming-Dou Ker. mr, 46(2-4):301-310, 2006. [doi]

2005

Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technologyShih-Hung Chen, Ming-Dou Ker. mr, 45(9-11):1311-1316, 2005. [doi]

A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage DeviceMing-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu. ieicet, 88-C(11):2150-2155, 2005. [doi]

MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS ProcessMing-Dou Ker, Kun-Hsien Lin, Che-Hao Chuang. ieicet, 88-C(3):429-436, 2005. [doi]

New curvature-compensation technique for CMOS bandgap reference with sub-1-V operationMing-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu. iscas 2005: 3861-3864 [doi]

Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applicationsMing-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai. iscas 2005: 1859-1862 [doi]

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structureKun-Hsien Lin, Ming-Dou Ker. iscas 2005: 1182-1185 [doi]

2004

A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signalsShih-Lun Chen, Ming-Dou Ker. iscas 2004: 573-576

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technologyChe-Hao Chuang, Ming-Dou Ker. iscas 2004: 577-580

Design optimization of ESD protection and latchup prevention for a serial I/O ICChih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker. mr, 44(2):213-221, 2004. [doi]

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage deviceMing-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu. iscas 2004: 41-44

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processesMing-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai. iscas 2004: 321-324

Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS ProcessesMing-Dou Ker, Wen-Yi Chen. isqed 2004: 445-450 [doi]

ESD protection design for IC with power-down-mode operationMing-Dou Ker, Kun-Hsien Lin. iscas 2004: 717-720

Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal LevelsMing-Dou Ker, Wei-Jen Chang, Wen-Yu Lo. isqed 2004: 433-438 [doi]

2003

Interference of ESD protection diodes on RF performance in Giga-Hz RF circuitsMing-Dou Ker, Chien-Ming Lee. iscas 2003: 297-300 [doi]

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface CircuitsMing-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng. isqed 2003: 363-368 [doi]

Active Device under Bond Pad to Save I/O Layout for High-pin-count SOCMing-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang. isqed 2003: 241 [doi]

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuitMing-Dou Ker, Chia-Sheng Tsai. iscas 2003: 97-100 [doi]

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC productI-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker. mr, 43(8):1295-1301, 2003. [doi]

Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset ICWen-Yu Lo, Ming-Dou Ker. mr, 43(9-11):1583-1588, 2003. [doi]

2002

2001

1999

ESD buses for whole-chip ESD protectionMing-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen. iscas 1999: 545-548 [doi]

1996

Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASICMing-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang. tvlsi, 4(3):307-321, 1996. [doi]

1995

Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC sMing-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu. iscas 1995: 833-836