Ming-Hung Chang - researchr alias

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Viewing Publication 1 - 28 from 28

2024

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank ArchitectureMasaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang. isscc 2024: 280-282 [doi]

2022

Speed control of electric vehicle by using type-2 fuzzy neural networkMing-Hung Chang, Yi-Chao Wu. mlc, 13(6):1647-1660, 2022. [doi]

A Unified Grey Riccati ModelMing-Feng Yeh, Ming-Hung Chang, Ching-Chuan Luo. axioms, 11(8):364, 2022. [doi]

2021

GM(1, 1;λ) with Constrained Linear Least SquaresMing-Feng Yeh, Ming-Hung Chang. axioms, 10(4):278, 2021. [doi]

2014

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOSChing-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang. asscc 2014: 145-148 [doi]

2013

2012

min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOSMing-Hung Chang, Yi-Te Chiu, Wei Hwang. tcas, 59-II(7):429-433, 2012. [doi]

2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOSMing-Hung Chang, Shang-Yuan Lin, Wei Hwang. jolpe, 8(1):63-72, 2012. [doi]

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operationMei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang. socc 2012: 5-10 [doi]

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANsWei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang. vlsi-dat 2012: 1-4 [doi]

Design of the Self-Constructing Fuzzy Neural Network controller for a sliding door systemHung-Ching Lu, Ming-Hung Chang. ijcnn 2012: 1-6 [doi]

Parameter estimation of fuzzy neural network controller based on a modified differential evolutionHung-Ching Lu, Ming-Hung Chang, Cheng-Hung Tsai. ijon, 89:178-192, 2012. [doi]

2011

2010

2009

A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithmYi-Ming Chang, Ming-Hung Chang, Wei Hwang. socc 2009: 115-118 [doi]

2008

A 300-mV 36-muW multiphase dual digital clock output generator with self-calibrationMing-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang. socc 2008: 97-100 [doi]

A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loopLi-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang. iscas 2008: 3342-3345 [doi]

2007

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