Noureddine Chabini - researchr alias

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Viewing Publication 1 - 42 from 42

2023

2022

2021

Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilizationMountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane. iet-cds, 15(5):475-484, 2021. [doi]

2020

Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW ArchitectureMohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini. jcsc, 29(12), 2020. [doi]

2017

2015

Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand addersNoureddine Chabini, Said Belkouch. aiccsa 2015: 1-4 [doi]

Reducing the number of embedded multipliers in squaring large size complex numbersFatima-Ezzahra Guessous, Noureddine Chabini. icm2 2015: 25-26 [doi]

2013

Design optimization of the quantization and a pipelined 2D-DCT for real-time applicationsAnas Hatim, Said Belkouch, Mohamed El Aakif, Moha M'rabet Hassani, Noureddine Chabini. mta, 67(3):667-685, 2013. [doi]

2012

An improved BCD adder using 6-LUT FPGAsShuli Gao, Dhamin Al-Khalili, Noureddine Chabini. newcas 2012: 13-16 [doi]

Asymmetric large size multipliers with optimised FPGA resource utilisationShuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois. iet-cdt, 6(6):372-383, 2012. [doi]

2011

Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction busNoureddine Chabini, Marilyn Wolf. iet-cdt, 5(5):386-392, 2011. [doi]

Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAsShuli Gao, Dhamin Al-Khalili, Noureddine Chabini. icecsys 2011: 137-140 [doi]

Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAsShuli Gao, Dhamin Al-Khalili, Noureddine Chabini. ipps 2011: 271-277 [doi]

2010

FPGA-Based Efficient Design Approaches for Large Size Two s Complement SquarersShuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois. vlsisp, 58(1):3-15, 2010. [doi]

2009

Two level decomposition based matrix multiplication for FPGAsShuli Gao, Dhamin Al-Khalili, Noureddine Chabini. icecsys 2009: 427-430 [doi]

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAsShuli Gao, Dhamin Al-Khalili, Noureddine Chabini. ijrc, 2009, 2009. [doi]

2007

An approach for computing the initial state for retimed synchronous sequential circuitsNoureddine Chabini, Wayne Wolf. hldvt 2007: 123-130 [doi]

A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential DesignsNoureddine Chabini. patmos 2007: 64-74 [doi]

Reducing the Code Size of Retimed Software Loops under Timing and Resource ConstraintsNoureddine Chabini, Wayne Wolf. wiess 2007: 255-268 [doi]

FPGA-Based Efficient Design Approach for Large-Size Two s Complement SquarersShuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois. asap 2007: 18-23 [doi]

Optimised realisations of large integer multipliers and squarers using embedded blocksShuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois. iet-cdt, 1(1):9-16, 2007. [doi]

2006

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded MultipliersShuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois. socc 2006: 21-24 [doi]

An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired MultipliersShuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois. aiccsa 2006: 248-254 [doi]

2005

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraintsNoureddine Chabini, Wayne Wolf. tvlsi, 13(10):1113-1126, 2005. [doi]

Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniquesNoureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria. todaes, 10(2):187-204, 2005. [doi]

2004

An approach for reducing dynamic power consumption in synchronous sequential digital designsNoureddine Chabini, Wayne Wolf. aspdac 2004: 198-204 [doi]

An approach for integrating basic retiming and software pipeliningNoureddine Chabini, Wayne Wolf. emsoft 2004: 287-296 [doi]

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scalingNoureddine Chabini, Wayne Wolf. tvlsi, 12(6):573-589, 2004. [doi]

2003

Minimizing Variables Lifetime in Loop-Intensive ApplicationsNoureddine Chabini, Wayne Wolf. emsoft 2003: 100-116 [doi]

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltagesNoureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria. tcad, 22(3):346-351, 2003. [doi]

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designsNoureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria. glvlsi 2003: 221-224 [doi]

2001

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniquesNoureddine Chabini, Yvon Savaria. isss 2001: 209-214

Determining Schedules for Reducing Power Consumption Using Multiple Supply VoltagesNoureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria. iccd 2001: 546-552

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