Peter Dahlgren - researchr alias

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Viewing Publication 1 - 20 from 20

2012

Social Media and Counter-Democracy: The Contingences of ParticipationPeter Dahlgren. epart 2012: 1-12 [doi]

2011

TM processorsLiang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson. itc 2011: 1-10 [doi]

2009

TM T2 familyLiang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu. itc 2009: 1-10 [doi]

2008

Transition Test on UltraSPARC- T2 MicroprocessorLiang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen. itc 2008: 1-10 [doi]

2005

Microprocessor silicon debug based on failure propagation tracingOlivier Caty, Peter Dahlgren, Ismet Bayraktaroglu. itc 2005: 10 [doi]

2003

Latch Divergency In Microprocessor Failure AnalysisPeter Dahlgren, Paul Dickinson, Ishwar Parulkar. itc 2003: 755-763 [doi]

1998

Switch-level bridging fault simulation in the presence of feedbacksPeter Dahlgren. itc 1998: 363-371 [doi]

1997

Switch-level modeling of feedback faults using global oscillation controlPeter Dahlgren. vts 1997: 117-122 [doi]

1996

Oscillation Control in Logic Simulation using Dynamic Dominance GrahpsPeter Dahlgren. dac 1996: 155-160 [doi]

A fault model for switch-level simulation of gate-to-drain shortsPeter Dahlgren, Peter Lidén. vts 1996: 414-421 [doi]

1995

A multiple-dominance switch-level model for simulation of short faultsPeter Dahlgren. iccad 1995: 674-680 [doi]

A Switch-level Algorithm for Simulation of Transients in Combinational LogicPeter Dahlgren, Peter Lidén. ftcs 1995: 207-216

Switch-Level Fault Simulation Based on Local AlgorithmsPeter Dahlgren. PhD thesis, Chalmers University of Technology, Gothenburg, Sweden, 1995. [doi]

Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS CheckersPeter Lidén, Peter Dahlgren. iscas 1995: 2124-2127

Switch-level modeling of transistor-level stuck-at faultsPeter Lidén, Peter Dahlgren. vts 1995: 208-215 [doi]

1994

Modeling of Intermediate Node States in switch-Level NetworksPeter Dahlgren, Peter Lidén. dac 1994: 722-727 [doi]

Using heavy-ion radiation to validate fault-handling mechanismsJohan Karlsson, Peter Lidén, Peter Dahlgren, Rolf Johansson, Ulf Gunneflo. micro, 14(1):8-23, 1994. [doi]

On Latching Probability of Particle Induced Transients in Combinational NetworksPeter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson. ftcs 1994: 340-349

1993

Efficient modeling of switch-level networks containing undetermined logic node statesPeter Dahlgren, Peter Lidén. iccad 1993: 746-752 [doi]

1992

Transistor Fault Coverage for Self-Testing CMOS CheckersPeter Lidén, Peter Dahlgren, Jan Torin. itc 1992: 476-485

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