Peter Pirsch - researchr alias

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2011

A FPGA architecture for real-time processing of variable-length FFTSStefan Langemeyer, Peter Pirsch, Holger Blume. icassp 2011: 1705-1708 [doi]

2010

Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementationChristian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch. samos 2010: 93-101 [doi]

Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD ResolutionHolger Flatt, Holger Blume, Peter Pirsch. reconfig 2010: 452-457 [doi]

A fully programmable FSM-based Processing Engine for Gigabytes/s header parsingKonstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer. samos 2010: 45-54 [doi]

A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architecturesGuillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch. asap 2010: 151-158 [doi]

A Multi-Shared Register File Structure for VLIW ProcessorsGuillermo PayÃ¡ VayÃ¡, Javier MartÃn-Langerwerf, Peter Pirsch. vlsisp, 58(2):215-231, 2010. [doi]

2009

Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architecturesHolger Flatt, Ingo Schmadecke, Mmichael Kärgel, Holger Blume, Peter Pirsch. samos 2009: 125-132 [doi]

An Enhanced DMA Controller in SIMD Processors for Video ApplicationsGuillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch. arcs 2009: 159-170 [doi]

2008

A parallel hardware architecture for connected component labeling based on fast label mergingHolger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch. asap 2008: 144-149 [doi]

On the Benefit of Caching Traffic Flow Data in the Link BufferKonstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch. samos 2008: 2-11 [doi]

2007

A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal ProcessingHolger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch. samos 2007: 241-250 [doi]

Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video CompressionNorman Nolte, Winfried Gehrke, Frank Wiczinowski, Peter Pirsch. icmcs 2007: 1187-1190 [doi]

ChipDesign: from theory to real worldGuillermo Payá Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch. wcae 2007: 58-64 [doi]

RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-ChipGuillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch. dsdm 2007: 215-221 [doi]

Design Space Exploration of Media Processors: A Parameterized SchedulerGuillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch. samos 2007: 41-49 [doi]

Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized SchedulerGuillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch. arcs 2007: 254-267 [doi]

2005

2004

2003

2002

Architecture of an Image Rendering Co-Processor for MPEG-4 Visual CompositingMladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo. vlsisp, 31(2):157-171, 2002. [doi]

Multicore system-on-chip architecture for MPEG-4 streaming videoMladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch. tcsv, 12(8):688, 2002.

Highly efficient simulation environment for HDTV video decoder in VLSI designXun Mao, Wei Wang, Huimin Gong, Yan L. He, Jian Lou, Lu Yu, Qingdong Yao, Peter Pirsch. vcip 2002: 1006-1014

Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing ApplicationsJavier Martín-Langerwerf, Carsten Reuter, Holger Kropp, Peter Pirsch. rsp 2002: 60-65 [doi]

Processor Architectures for Multimedia ApplicationsPeter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg. samos 2002: 188-206 [doi]

2001

2000

Architecture of an Image Rendering Co-Processor for MPEG-4 SystemsMladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo. asap 2000: 15-24 [doi]

Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated CircuitKlaus Herrmann, Sören Moch, Jörg Hilgenstock, Peter Pirsch. dft 2000: 105-113 [doi]

Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes)Carsten Reuter, Holger Kropp, Peter Pirsch. it, 42(3):5-9, 2000. [doi]

Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, ProceedingsDimitrios Soudris, Peter Pirsch, Erich Barke, editors, Volume 1918 of Lecture Notes in Computer Science, Springer, 2000.

1999

Instruction Set Extensions for MPEG-4 VideoMladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack. vlsisp, 23(1):27-49, 1999. [doi]

Hardware Realization of a Java Virtual Machine for High Performance Multimedia ApplicationsMladen Berekovic, Helge Kloos, Peter Pirsch. vlsisp, 22(1):31-43, 1999. [doi]

Architecture of a hardware module for MPEG-4 shape decodingMladen Berekovic, K. Jacob, Peter Pirsch. iscas 1999: 157-160 [doi]

Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAMJörg Hilgenstock, Klaus Herrmann, Peter Pirsch. glvlsi 1999: 42-45 [doi]

Guest Editors IntroductionMohammad Ibrahim, Peter Pirsch, Johan McCanny. vlsisp, 22(1):5-6, 1999. [doi]

Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-AnwendungenHelge Kloos, Mladen Berekovic, Peter Pirsch. arcs 1999: 5-14

An FPGA-based Prototyping System for Real-Time Verification of Video Processing SchemesHolger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch. fpl 1999: 333-338

Cellular Multiprocessor Arrays with Adaptive Resource UtilizationHans-Joachim Stolberg, Martin Ohmacht, Peter Pirsch. acpc 1999: 480-489 [doi]

HiPAR-DSP: Ein 1.3 GOPS Multimedia SignalprozessorJens Peter Wittenburg, Willm Hinrichs, Martin Ohmacht, Hanno Lieske, Helge Kloos, Peter Pirsch. arcs 1999: 15-21

1998

An Algorithm-Hardware-System Approach to VLIW Multimedia ProcessorsMladen Berekovic, Peter Pirsch, Johannes Kneip. vlsisp, 20(1-2):163-180, 1998. [doi]

An Array Processor Architecture with Parallel Data Cache for Image Rendering and CompositingMladen Berekovic, Peter Pirsch. icgi 1998: 411 [doi]

A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAsTien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch. fpl 1998: 441-445 [doi]

A Video Signal Processor for MIMD MultiprocessingJörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch. dac 1998: 50-55 [doi]

The Video and Image Processing Emulation System VIPESHolger Kropp, Carsten Reuter, Peter Pirsch. rsp 1998: 170-175 [doi]

Architectures for digital signal processingPeter Pirsch. Wiley, 1998.

Realization of a Programmable Parallel DSP for High Performance Image Processing ApplicationsJens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch. dac 1998: 56-61 [doi]

1997

1996

Architekturen der digitalen SignalverarbeitungPeter Pirsch. Informationstechnik, Teubner, 1996.

1995

Architecture and C++-programming environment of a highly parallel image signal processorJohannes Kneip, Martin Ohmacht, Karsten RÃ¶nner, Peter Pirsch. jsa, 41(5-6):391-408, 1995. [doi]

Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal ProcessorPeter Pirsch, Johannes Kneip, Karsten Rönner. iscas 1995: 562-565

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemesMarkus Schwiegershausen, Peter Pirsch. eurodac 1995: 8-13 [doi]

A system level design methodology for the optimization of heterogeneous multiprocessorsMarkus Schwiegershausen, Peter Pirsch. isss 1995: 162-169 [doi]

The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniquesMirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner. vlsisp, 11(1-2):51-74, 1995. [doi]

Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMsMarco Winzker, Peter Pirsch, Jochen Reimers. iscas 1995: 609-612

1993

1991

Synthesis of Intermediate Memories needed for the Data Supply to Processor ArraysMirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch. vlsi 1992: 297-306

Synthesis of intermediate memories for the data supply to processor arraysMirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch. ccc 1992: 365-370

1984

Circuit Technique for VLSI Design of a Video CodecP. Drews, Peter Pirsch, K. Schaper. icc 1984: 250-255

1983

Transmission of gray level images by multilevel dither techniquesPeter Pirsch, Arun N. Netravali. cg, 7(1):31-44, 1983. [doi]