Pradip Bose - researchr alias

researchr

You are not signed in
Sign in
Sign up

2011

Keynote II: Integrated modeling challenges in extreme-scale computingPradip Bose. ispass 2011: 133 [doi]

Introducing the Adaptive Energy Management Features of the Power7 ChipMichael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu. micro, 31(2):60-75, 2011. [doi]

Adaptive energy-management features of the IBM POWER7 chipMichael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, Juan C. Rubio, Birgit Schubert, Bruno Spruth, José A. Tierno, Lorena Pesantez. ibmrd, 55(3):8, 2011. [doi]

Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundaryAmlan Ganguly, Partha Kundu, Pradip Bose. nocs 2011: 241-246 [doi]

Abstraction and microarchitecture scaling in early-stage power modelingHans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer. hpca 2011: 394-405 [doi]

Energy-Aware Accounting and Billing in Large-Scale Computing FacilitiesVictor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero. micro, 31(3):60-71, 2011. [doi]

A case for guarded power gating for multi-core processorsNiti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram. hpca 2011: 291-300 [doi]

Error Tolerance in Server Class ProcessorsJude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose. tcad, 30(7):945-959, 2011. [doi]

2010

Power-efficient, reliable microprocessor architectures: modeling and design methodsPradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban. glvlsi 2010: 299-304 [doi]

16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 9-14 January 2010, Bangalore, IndiaMatthew T. Jacob, Chita R. Das, Pradip Bose, editors, IEEE Computer Society, 2010.

Trends and techniques for energy efficient architecturesVictor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero. vlsi 2010: 276-279 [doi]

Power and thermal characterization of POWER6 systemVictor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose. IEEEpact 2010: 7-18 [doi]

Performance and power evaluation of an in-line acceleratorAlejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose. cf 2010: 81-82 [doi]

2009

2008

Exploring power management in multi-core systemsReinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer. aspdac 2008: 708-713 [doi]

Online Estimation of Architectural Vulnerability Factor for Soft ErrorsXiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers. isca 2008: 341-352 [doi]

Metrics for Architecture-Level Lifetime Reliability AnalysisPradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers. ispass 2008: 202-212 [doi]

Phaser: Phased methodology for modeling the system-level effects of soft errorsJude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves. ibmrd, 52(3):293-306, 2008. [doi]

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM LifetimeJeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston. isca 2008: 353-362 [doi]

2007

Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshopAneesh Aggarwal, Pradip Bose, Mohamed Zahran. sigarch, 35(3):1, 2007. [doi]

Performance modeling for early analysis of multi-core systemsReinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han. codes 2007: 209-214 [doi]

Thermal-aware task scheduling at the system software levelJeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Henrdrik Hamann, Alan J. Weger, Pradip Bose. islped 2007: 213-218 [doi]

Temperature-limited microprocessors: Measurements and design implicationsHendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil. vlsid 2007: 427-432 [doi]

Architecture-Level Soft Error Analysis: Examining the Limits of Common AssumptionsXiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers. dsn 2007: 266-275 [doi]

Evaluating design tradeoffs in on-chip power management for CMPsJoseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose. islped 2007: 44-49 [doi]

A Framework for Architecture-Level Lifetime Reliability ModelingJeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose. dsn 2007: 534-543 [doi]

Low-Power Design and Temperature ManagementKevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou. micro, 27(6):46-57, 2007. [doi]

2006

2005

The power of communicationPradip Bose. micro, 25(1):5, 2005. [doi]

Integrated microarchitecturesPradip Bose. micro, 25(3):5-6, 2005. [doi]

High performance at affordable powerPradip Bose. micro, 25(5):5, 2005. [doi]

Designing microprocessors with robust functionality and performancePradip Bose. micro, 25(6):5, 2005. [doi]

Power-Aware, Reliable Microprocessor DesignPradip Bose. vlsid 2005: 3 [doi]

Variation-tolerant designPradip Bose. micro, 25(2):5, 2005. [doi]

Presilicon modeling: challenges in the late CMOS eraPradip Bose. micro, 25(4):5-6, 2005. [doi]

Stretching the Limits of Clock-Gating Efficiency in Server-Class ProcessorsHans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler. hpca 2005: 238-242 [doi]

SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft ErrorsXiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers. dsn 2005: 496-505 [doi]

Exploiting Structural Duplication for Lifetime Reliability EnhancementJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. isca 2005: 520-531 [doi]

Lifetime Reliability: Toward an Architectural SolutionJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. micro, 25(3):70-80, 2005. [doi]

Guest Editors Introduction: Energy-Efficient DesignKunio Uchiyama, Pradip Bose. micro, 25(5):6-9, 2005. [doi]

2004

Communication versus ComputationPradip Bose. micro, 24(5):5, 2004. [doi]

Editor in Chief s Message: Saving power-Lessons from embedded systemsPradip Bose. micro, 24(4):5-6, 2004. [doi]

EIC s Message: General-purpose versus application-specific processorsPradip Bose. micro, 24(3):5, 2004. [doi]

Editor in Chief s Message: New Challenges and Burning IssuesPradip Bose. micro, 24(1):5, 2004. [doi]

EIC s Message: Chip-level microarchitecture trendsPradip Bose. micro, 24(2):5, 2004. [doi]

Computer architecture research: Shifting priorities and newer challengesPradip Bose. micro, 24(6):5, 2004. [doi]

Power-performance simulation: design and validation strategiesDavid Brooks, Pradip Bose, Margaret Martonosi. sigmetrics, 31(4):13-18, 2004. [doi]

Microarchitectural techniques for power gating of execution unitsZhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose. islped 2004: 32-37 [doi]

Understanding the energy efficiency of simultaneous multithreadingYingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose. islped 2004: 44-49 [doi]

The Impact of Technology Scaling on Lifetime ReliabilityJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. dsn 2004: 177 [doi]

The Case for Lifetime Reliability-Aware MicroprocessorsJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. isca 2004: 276-287 [doi]

Integrated Analysis of Power and Performance for Pipelined MicroprocessorsVictor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma. TC, 53(8):1004-1016, 2004. [doi]

2003

Dynamically Tuning Processor Resources with Adaptive ProcessingDavid H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster. Computer, 36(12):49-58, 2003. [doi]

Editor-in-Chief?s Message: Adapting Old Paradigms to Meet New ChallengesPradip Bose. micro, 23(4):5, 2003. [doi]

Looking Forward to Bright New BeginningsPradip Bose. micro, 23(1):5-6, 2003. [doi]

Issues and Trends in High-Performance Processor CoresPradip Bose. micro, 23(2):5, 2003. [doi]

Guest Editors Introduction: Power and Complexity Aware DesignPradip Bose, David H. Albonesi, Diana Marculescu. micro, 23(5):8-11, 2003. [doi]

Design and Integration: Chip- and System-Level ChallengesPradip Bose. micro, 23(3):5, 2003. [doi]

New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessorsDavid Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield. ibmrd, 47(5-6):653-670, 2003. [doi]

Energy Efficient Co-Adaptive Instruction Fetch and IssueAlper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose. isca 2003: 147-156 [doi]

Guest Editors Introduction: Micro s Top Picks from Microarchitecture ConferencesCharles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose. micro, 23(6):8-10, 2003. [doi]

2002

Early-Stage Definition of LPX: A Low Power Issue-Execute ProcessorPradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas. pacs 2003: 1-17 [doi]

Tradeoffs in power-efficient issue queue designAlper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster. islped 2002: 184-189 [doi]

Synchronous Interlocked PipelinesHans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster. async 2002: 3-12 [doi]

Saving energy with just in time instruction deliveryTejas Karkhanis, James E. Smith, Pradip Bose. islped 2002: 178-183 [doi]

Optimizing pipelines for power and performanceViji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma. euromicro 2002: 333-344 [doi]

2001

Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance ValidationPradip Bose. dsn 2001: 481-486 [doi]

A circuit level implementation of an adaptive issue queue for power-aware microprocessorsAlper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook. glvlsi 2001: 73-78 [doi]

2000

Performance and Functional Verification of MicroprocessorsPradip Bose, Jacob A. Abraham. vlsid 2000: 58-63 [doi]

Testing for Function and Performance: Towards an Integrated Processor Validation MethodologyPradip Bose. et, 16(1-2):29-48, 2000. [doi]

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation MicroprocessorsDavid Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook. micro, 20(6):26-44, 2000. [doi]

Power-Performance Modeling and Tradeoff Analysis for a High End MicroprocessorDavid Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose. pacs 2001: 126-136 [doi]

An Adaptive Issue Queue for Reduced Power at High PerformanceAlper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi. pacs 2001: 25-39 [doi]

1999

Performance Evaluation and Validation of MicroprocessorsPradip Bose. sigmetrics 1999: 226-227 [doi]

Bounds modelling and compiler optimizations for superscalar performance tuningPradip Bose, Sunil Kim, Francis P. O Connell, William A. Ciarfella. jsa, 45(12-13):1111-1137, 1999. [doi]

1998

Performance Test Case Generation for MicroprocessorsPradip Bose. vts 1998: 54-61 [doi]

Performance Analysis and Its Impact on DesignPradip Bose, Thomas M. Conte. Computer, 31(5):41-49, 1998.

1997

PrefacePradip Bose. ibmrd, 41(3):204-204, 1997. [doi]

Accuracy and Speedup of Parallel Trace-Driven Architectural SimulationAnthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael. ipps 1997: 39-44 [doi]

1996

Representative Traces for Processor Models with Infinite CacheVijay S. Iyengar, Louise Trevillyan, Pradip Bose. hpca 1996: 62-72 [doi]

1995

Architectural timing verification of CMOS RISC processorsPradip Bose, S. Surya. ibmrd, 39(1-2):113-130, 1995.

1994

Architectural Timing Verification and Test for Super Scalar ProcessorsPradip Bose. ftcs 1994: 256-265

Architectural Performance Verification: PowerPC:::TM::: ProcessorsS. Surya, Pradip Bose, Jacob A. Abraham. iccd 1994: 344-347

1993

MIPS-Driven Early Design and Analysis of VLSI CPU ChipsPradip Bose, John-David Wellman. vlsid 1993: 256-259

1992

Workload-Driven Floorplanning for MIPS OptimizationPradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim. iccd 1992: 387-391

1991

Early Performance Estimation of Super Scalar Machine ModelsPradip Bose. iccd 1991: 388-392

1988

Interactive program improvement via EAVE: an expert adviser for vectorizationPradip Bose. ics 1988: 119-130 [doi]

A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation ProblemPradip Bose. TC, 37(12):1569-1577, 1988.

Parallel Simulation and Test of VLSI Array LogicPradip Bose. awoc 1988: 301-311

Heuristic Rule-Based Program Transformations for Enhanced VectorizationPradip Bose. icpp 1988: 63-66

1986

Optimal Code Generation for Expressions on Super Scalar MachinesPradip Bose. fjcc 1986: 372-379

PreviousNext