R. Venkatraman - researchr alias

researchr

You are not signed in
Sign in
Sign up

2009

2006

Enabling Quality and Schedule Predictability in SoC Design using HandoffQCBhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao. isqed 2006: 769-774 [doi]

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and StabilityR. Venkatraman, R. Castagnetti, S. Ramesh. isqed 2006: 190-195 [doi]

2005

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoCR. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh. isqed 2005: 193-196 [doi]

2003

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and ManufacturabilityF. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh. isqed 2003: 119-124 [doi]

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-SiliconKaranth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji. vlsid 2002: 781-788 [doi]

2000

An evolutionary approach to timing driven FPGA placementR. Venkatraman, Lalit M. Patnaik. glvlsi 2000: 81-85 [doi]

Rule-based system application for a technical problem in inventory issueR. Venkatraman, S. Venkatraman. aei, 14(2):143-152, 2000. [doi]