Rajeev Jain - researchr alias

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Viewing Publication 1 - 50 from 50

2023

An Automation Framework for Comparison of Cancer Response Models Across ConfigurationsJustin M. Wozniak, Rajeev Jain, Andreas Wilke, Rylie Weaver, Alexander Partin, Thomas S. Brettin, Rick Stevens. eScience 2023: 1-10 [doi]

2022

Exascale models of stellar explosions: Quintessential multi-physics simulationJames Austin Harris, Ran Chu, Sean M. Couch, Anshu Dubey, Eirik Endeve, Antigoni Georgiadou, Rajeev Jain, Daniel Kasen, M. Paul Laiu, O. E. Bronson Messer, Jared O'Neal, Michael A. Sandoval, Klaus Weide. ijhpca, 36(1):59-77, 2022. [doi]

Accelerating Flash-X Simulations with Asynchronous I/ORajeev Jain, Houjun Tang, Akash Dhruv, James Austin Harris, Suren Byna. pdsw 2022: 13-19 [doi]

From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologiesChristopher Patrick, S. C. Song, Irfan Khan, Nader Nikfar, Matt Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain. vlsit 2022: 1-2 [doi]

Automated Design of Analog Circuits Using Reinforcement LearningKeertana Settaluri, Zhaokai Liu, Rishubh Khurana, Arash Mirhaj, Rajeev Jain, Borivoje Nikolic. tcad, 41(9):2794-2807, 2022. [doi]

2021

Fast and Accurate PPA Modeling with Transfer LearningW. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain. iccad 2021: 1-8 [doi]

2020

Data-driven CAD or Algorithm-Driven CAD: Competitors or Collaborators?Rajeev Jain, Pankaj Kukkal. mlcad 2020: 69 [doi]

2018

2017

Kano integrated robust design approach for aesthetical product design: a case study of a car profileH. C. Yadav, Rajeev Jain, A. R. Singh, P. K. Mishra. jim, 28(7):1709-1727, 2017. [doi]

2014

A Kano model, AHP and M-TOPSIS method-based technique for disassembly line balancing under fuzzy environmentShwetank Avikal, Rajeev Jain, P. K. Mishra. asc, 25:519-529, 2014. [doi]

Using data mining synergies for evaluating criteria at pre-qualification stage of supplier selectionRajeev Jain, A. R. Singh, H. C. Yadav, P. K. Mishra. jim, 25(1):165-175, 2014. [doi]

2013

A heuristic approach for U-shaped assembly line balancing to improve labor productivityShwetank Avikal, Rajeev Jain, P. K. Mishra, H. C. Yadav. candie, 64(4):895-901, 2013. [doi]

PostBL: Post-mesh Boundary Layer Mesh Generation ToolRajeev Jain, Timothy J. Tautges. imr 2014: 331-348 [doi]

2012

A New Heuristic for Disassembly Line Balancing Problems with AND/OR Precedence RelationsShwetank Avikal, Rajeev Jain, Harish Yadav, P. K. Mishra. socpros 2014: 519-525 [doi]

Creating geometry and mesh models for nuclear reactor core geometries using a lattice hierarchy-based approachTimothy J. Tautges, Rajeev Jain. ewc, 28(4):319-329, 2012. [doi]

2010

Creating Geometry and Mesh Models for Nuclear Reactor Core Geometries Using a Lattice Hierarchy-Based ApproachTimothy J. Tautges, Rajeev Jain. imr 2010: 351-365 [doi]

2009

Spectrum Sensing Design Framework Based on Cross-Layer Optimization of Detection EfficiencyJiHoon Park, Rajeev Jain, Danijela Cabric. icc 2009: 1-6 [doi]

1999

DEFACTO: A Design Environment for Adaptive Computing TechnologyKiran Bondalapati, Pedro C. Diniz, Phillip Duncan, John J. Granacki, Mary W. Hall, Rajeev Jain, Heidi E. Ziegler. ipps 1999: 570-578

Adaptive radio for multimedia wireless linksCharles Chien, Mani B. Srivastava, Rajeev Jain, Paul Lettieri, Vipin Aggarwal, Robert Sternowski. jsac, 17(5):793-813, 1999. [doi]

1998

Panel: Challenges for Future Systems on a ChipRajeev Jain. vlsid 1998: 578

Simulation and Synthesis of VLSI Communication SystemsRajeev Jain, Charles Chien, Etan G. Cohen, Leader Ho. vlsid 1998: 336-341 [doi]

A 110-K transistor 25-MPixels/s configurable image transform processor unitStephen Molloy, Rajeev Jain. jssc, 33(1):86-97, 1998. [doi]

1997

On-line broadcast archives for interactive videoH. O. Srivastava, Rajeev Jain. tbc, 43(3):288-308, 1997. [doi]

1996

1995

Strategies for design automation of high speed digital filtersPhillip Duncan, Ken Kindsfater, Lynette Liu, Rajeev Jain. vlsisp, 9(1-2):105-119, 1995. [doi]

Techniques for FPGA Implementation of Video Compression SystemsBrian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain. fpga 1995: 154-159 [doi]

1994

A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 /spl mu/m CMOSCharles Chien, Rajeev Jain, Etan G. Cohen, Henry Samueli. jssc, 29(12):1614-1623, December 1994. [doi]

An Algorithm-Driven Processor Design for Video CompressionSteve Molloy, Brian Schoner, Avanindra Madisetti, Rajeev Jain, Roy Matic. icip 1994: 611-615

1993

Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver ArchitectureBong-Young Chung, Charles Chien, Henry Samueli, Rajeev Jain. jsac, 11(7):1096-1107, 1993.

An Integrated Technology CAD System for Process and Device DesignersK. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli. vlsid 1993: 287-292

1992

Hi-PASS: a computer-aided synthesis system for maximally parallel digital signal processing ASICsPhilip Duncan, Shobana Swamy, Steve Sprouse, Daniel Potasz, Rajeev Jain, Neal M. Gafter, William Cammack, Yiwan Wong, Wanda Gass. icassp 1992: 605-608 [doi]

Decimation filter compiler for oversampling A/D applicationsSoei-Shin Hang, Rajeev Jain. icassp 1992: 537-540 [doi]

An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controllerRajeev Jain, Avanindra Madisetti, Richard L. Baker. tcsv, 2(2):147-158, 1992. [doi]

DDFSGENLinda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen. vlsisp, 4(2-3):213-226, 1992. [doi]

Architectures and integrated circuits for real time vector quantization of imagesAvanindra Madisetti, Rajeev Jain, Richard L. Baker, Raffi Dianysian. icassp 1992: 677-680 [doi]

Real Time Implementation of Pruned Tree Search Vector QuantizationAvanindra Madisetti, Rajeev Jain, R. L. Baker. dcc 1992: 152-161

1991

1990

A functional silicon compiler for high speed FIR digital filtersPaul T. Yang, Rajeev Jain, Toshiaki Yoshino, Wanda Gass, Ashwin Shah. icassp 1990: 1329-1332 [doi]

1989

FDT-a design tool for switched capacitor filtersSattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild. iccad 1989: 446-449 [doi]

1988

An ASIC architecture for contour line filteringFrancky Catthoor, Lawrence O'Gorman, Rajeev Jain. icassp 1988: 1056-1059 [doi]

Architectural strategies for an application-specific synchronous multiprocessor environmentFrancky Catthoor, Jan M. Rabaey, Gert Goossens, Jef L. van Meerbergen, Rajeev Jain, Hugo J. De Man, Joos Vandewalle. tsp, 36(2):265-284, 1988. [doi]

1986

A fast adder-based multiplication unit for customised digital signal processorsLuc De Vos, Rajeev Jain, Hugo De Man, Walter Ulbrich. icassp 1986: 2163-2166 [doi]

1985

CAD Tools for the optimized design of custom VLSI wave digital filtersRajeev Jain, Gert Goossens, Luc J. M. Claesen, Joos Vandewalle, Hugo De Man, L. Gazsi, A. Fettweis. icassp 1985: 1465-1468 [doi]

1984

Efficient CAD tools for the coefficient optimisation of arbitrary integrated digital filtersRajeev Jain, Joos Vandewalle, Hugo De Man. icassp 1984: 602-605 [doi]

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