Roberto R. Osorio - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 30 from 30

2023

Implementation of a motion estimation algorithm for Intel FPGAs using OpenCLManuel de Castro, Roberto R. Osorio, David López Vilariño, Arturo González-Escribano, Diego R. Llanos. tjs, 79(9):9866-9888, June 2023. [doi]

Floating Point Calculation of the Cube Function on FPGAsRoberto R. Osorio. tpds, 34(1):372-382, 2023. [doi]

2022

An efficient ant colony optimization framework for HPC environmentsPatricia González, Roberto R. Osorio, Xoán C. Pardo, Julio R. Banga, Ramón Doallo. asc, 114:108058, 2022. [doi]

2019

Hardware Implementation of Statecharts for FPGA-based Control in Scientific FacilitiesJavier Cereijo García, Roberto R. Osorio. dcis 2019: 1-6 [doi]

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable ProcessorsRoberto R. Osorio, Gabriel Rodríguez 0001. access, 7:56353-56366, 2019. [doi]

2016

A fast algorithm for constructing nearly optimal prefix codesRoberto R. Osorio, Patricia González. SPE, 46(10):1299-1316, 2016. [doi]

Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley modelRoberto R. Osorio. asap 2016: 202-206 [doi]

2013

Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint SizesIván Cores, Gabriel Rodríguez, María J. Martín, Patricia González, Roberto R. Osorio. ngc, 31(3):163-185, 2013. [doi]

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC StandardRoberto R. Osorio, Javier D. Bruguera. vlsisp, 72(2):119-132, 2013. [doi]

Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage NetworksAngela Souto Vieites, Roberto R. Osorio. dsd 2013: 799-802 [doi]

2012

Fast Construction of Nearly-Optimal Prefix Codes without Probability SortingRoberto R. Osorio, Patricia González. dcc 2012: 407 [doi]

2011

Performance analysis of massively parallel embedded hardware architectures for retinal image processingAlejandro Nieto, Victor M. Brea, David López Vilariño, Roberto R. Osorio. ejivp, 2011:10, 2011. [doi]

2009

A digital cellular-based system for retinal vessel-tree extractionCesar Diaz-Resco, Alejandro Nieto, Roberto R. Osorio, Victor M. Brea, David López Vilariño. ecctd 2009: 835-838 [doi]

High Performance Image Processing on a Massively Parallel Processor ArrayRoberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera. dsd 2009: 233-236 [doi]

2008

An FPGA architecture for CABAC decoding in manycore systemsRoberto R. Osorio, Javier D. Bruguera. asap 2008: 293-298 [doi]

2007

Entropy Coding on a Programmable Processor Array for Multimedia SoCRoberto R. Osorio, Javier D. Bruguera. asap 2007: 222-227 [doi]

2006

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost QuantizationJavier D. Bruguera, Roberto R. Osorio. dsdm 2006: 407-414 [doi]

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded SystemsRoberto R. Osorio, Javier D. Bruguera. dsdm 2006: 269-274 [doi]

High-Throughput Architecture for H.264/AVC CABAC Compression SystemRoberto R. Osorio, Javier D. Bruguera. tcsv, 16(11):1376-1384, 2006. [doi]

2005

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video CoderRoberto R. Osorio, Javier D. Bruguera. dsdm 2005: 298-305 [doi]

2004

View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture codingGauthier Lafruit, Eric Delfosse, Roberto R. Osorio, Wolfgang van Raemdonck, V. Ferentinos. tcsv, 14(7):1021-1031, 2004. [doi]

Arithmetic Coding Architecture for H.264/AVC CABAC Compression SystemRoberto R. Osorio, Javier D. Bruguera. dsdm 2004: 62-69 [doi]

2003

High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based CompressionRoberto R. Osorio, Bart Vanhoof. vlsisp, 33(3):267-275, 2003. [doi]

2002

Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streamingRoberto R. Osorio, Sylvain Devillers, Eric Delfosse, Myriam Amielh, Gauthier Lafruit. icip 2002: 17-20

2000

Architectures for arithmetic coding in image compressionRoberto R. Osorio, Javier D. Bruguera. eusipco 2000: 1-4 [doi]

1999

New model for arithmetic coding/decoding of multilevel images based on a cache memoryRoberto R. Osorio, Javier D. Bruguera. icecsys 1999: 697-700 [doi]

1998

Arithmetic Image Coding/Decoding Architecture Based on a Cache MemoryRoberto R. Osorio, Montserrat Bóo, Javier D. Bruguera. euromicro 1998: 10139 [doi]

1997

New arithmetic coder/decoder architectures based on pipeliningRoberto R. Osorio, Javier D. Bruguera. asap 1997: 106-115 [doi]

A VLSI implementation of an arithmetic coder for image compressionMercedes Péon, Roberto R. Osorio, Javier D. Bruguera. euromicro 1997: 591 [doi]

1995

Digit On-line Large Radix CORDIC RotatorRoberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata. asap 1995: 246-257 [doi]

Sign in or sign up to see more results.

runs on WebDSL