Rolf Drechsler - researchr alias

researchr

You are not signed in
Sign in
Sign up

2012

Foreword: Special Issue on Reversible ComputationRolf Drechsler, Irek Ulidowski, Robert Wille. mvl, 18(1):1-3, 2012. [doi]

RevKit: A Toolkit for Reversible Circuit DesignMathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler. mvl, 18(1):55-65, 2012. [doi]

2011

Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part IICecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Neil Urquhart, A. Sima Etaner-Uyar, editors, Volume 6625 of Lecture Notes in Computer Science, Springer, 2011. [doi]

Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary AlgorithmsRolf Drechsler, Alexander Finder, Robert Wille. evoW 2011: 151-161 [doi]

Effective Robustness Analysis Using Bounded Model Checking TechniquesGörschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler. tcad, 30(8):1239-1252, 2011. [doi]

Simulation-based equivalence checking between SystemC models at different levels of abstractionDaniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler. glvlsi 2011: 223-228 [doi]

Encoding OCL Data Types for SAT-Based Verification of UML/OCL ModelsMathias Soeken, Robert Wille, Rolf Drechsler. tap 2011: 152-170 [doi]

ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean OptimizationRobert Wille, Hongyan Zhang, Rolf Drechsler. isvlsi 2011: 120-125 [doi]

Debugging reversible circuitsRobert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler. integration, 44(1):51-61, 2011. [doi]

2010

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitationStephan Eggersglüß, Daniel Tille, Rolf Drechsler. iscas 2010: 649-652 [doi]

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued LogicsStephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler. et, 26(3):307-322, 2010. [doi]

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits)Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler. it, 52(4):216-223, 2010. [doi]

An Evolutionary Algorithm for Optimization of Pseudo Kronecker ExpressionsAlexander Finder, Rolf Drechsler. ismvl 2010: 150-155 [doi]

RobuCheck: A Robustness Checker for Digital CircuitsStefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler. dsd 2010: 226-231 [doi]

Efficient Simulation-Based Debugging of Reversible LogicStefan Frehse, Robert Wille, Rolf Drechsler. ismvl 2010: 156-161 [doi]

Proving transaction and system-level properties of untimed SystemC TLM designsDaniel Große, Hoang M. Le, Rolf Drechsler. memocode 2010: 113-122 [doi]

Polynomial datapath optimization using constraint solving and formal modellingFinn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler. iccad 2010: 756-761 [doi]

Enhancing debugging of multiple missing control errors in reversible logicJean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler. glvlsi 2010: 465-470 [doi]

Towards analyzing functional coverage in SystemC TLM property checkingHoang M. Le, Daniel Große, Rolf Drechsler. hldvt 2010: 67-74 [doi]

Reducing Reversible Circuit Cost by Adding LinesD. Michael Miller, Robert Wille, Rolf Drechsler. ismvl 2010: 217-222 [doi]

Debugging at the Electronic System LevelFrank Rogin, Rolf Drechsler. Springer, 2010. [doi]

Verifying UML/OCL models using Boolean satisfiabilityMathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler. date 2010: 1341-1344 [doi]

Using QBF to increase accuracy of SAT-based debuggingAndré Sülflow, Görschwin Fey, Rolf Drechsler. iscas 2010: 641-644 [doi]

Incremental Solving Techniques for SAT-based ATPGDaniel Tille, Stephan Eggersglüß, Rolf Drechsler. tcad, 29(7):1125-1130, 2010. [doi]

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDsDaniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler. ets 2010: 176-181 [doi]

Reducing the number of lines in reversible circuitsRobert Wille, Mathias Soeken, Rolf Drechsler. dac 2010: 647-652 [doi]

Synthese reversibler Logik (Synthesizing Reversible Logic)Robert Wille, Rolf Drechsler. it, 52(1):30-38, 2010. [doi]

Effect of BDD Optimization on Synthesis of Reversible and Quantum LogicRobert Wille, Rolf Drechsler. ENTCS, 253(6):57-70, 2010. [doi]

SyReC: A Programming Language for Synthesis of Reversible CircuitsRobert Wille, Sebastian Offermann, Rolf Drechsler. fdl 2010: 184-189

BDD-Based Synthesis of Reversible LogicRobert Wille, Rolf Drechsler. ijamc-igi, 1(4):25-41, 2010. [doi]

Towards a Design Flow for Reversible LogicRobert Wille, Rolf Drechsler. Springer, 2010. [doi]

2009

Non-Clausal SAT and ATPGRolf Drechsler, Tommi A. Junttila, Ilkka NiemelÃ¤. In Armin Biere, Marijn Heule, Hans van Maaren, Toby Walsh, editors, Handbook of Satisfiability. Volume 185 of Frontiers in Artificial Intelligence and Applications, pages 655-693, IOS Press, 2009. [doi]

Effiziente ErfÃ¼llbarkeitsalgorithmen fÃ¼r die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation)Rolf Drechsler, Stephan EggersglÃ¼ÃŸ, GÃ¶rschwin Fey, JÃ¼rgen SchlÃ¶ffel, Daniel Tille. it, 51(2):102-111, 2009. [doi]

Test Pattern Generation using Boolean Proof EnginesRolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille. Springer, 2009. [doi]

Approximate BDD Minimization by Weighted ARüdiger Ebendt, Rolf Drechsler. iscas 2009: 2974-2977 [doi]

Weighted A:::*::: search - unifying view and applicationRÃ¼diger Ebendt, Rolf Drechsler. ai, 173(14):1310-1342, 2009. [doi]

Speeding up SAT-Based ATPG Using Dynamic Clause ActivationStephan EggersglÃ¼ÃŸ, Daniel Tille, Rolf Drechsler. ats 2009: 177-182 [doi]

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning TechniquesStephan Eggersglüß, Rolf Drechsler. ets 2009: 81-86 [doi]

Computing bounds for fault tolerance using formal techniquesGÃ¶rschwin Fey, AndrÃ© SÃ¼lflow, Rolf Drechsler. dac 2009: 190-195 [doi]

Robustness Check for Multiple Faults Using Formal TechniquesStefan Frehse, GÃ¶rschwin Fey, AndrÃ© SÃ¼lflow, Rolf Drechsler. dsd 2009: 85-90 [doi]

Overcoming limitations of the SystemC data introspectionChristian Genz, Rolf Drechsler. date 2009: 590-593 [doi]

Exact Synthesis of Elementary Quantum Gate CircuitsDaniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. mvl, 15(4):283-300, 2009. [doi]

Induction-Based Formal Verification of SystemC TLM DesignsDaniel Große, Hoang M. Le, Rolf Drechsler. mtv 2009: 101-106 [doi]

Contradictory antecedent debugging in bounded model checkingDaniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler. glvlsi 2009: 173-176 [doi]

Exact Multiple-Control Toffoli Network Synthesis With SAT TechniquesDaniel GroÃŸe, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. tcad, 28(5):703-715, 2009. [doi]

Property analysis and design understandingUlrich KÃ¼hne, Daniel GroÃŸe, Rolf Drechsler. date 2009: 1246-1249 [doi]

Timing Arc based logic analysis for false noise reductionMurthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler. iccad 2009: 225-230 [doi]

Advanced verification by automatic property generationFrank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke. iet-cdt, 3(4):338-353, 2009. [doi]

WoLFram- A Word Level Framework for Formal VerificationAndrÃ© SÃ¼lflow, Ulrich KÃ¼hne, GÃ¶rschwin Fey, Daniel GroÃŸe, Rolf Drechsler. rsp 2009: 11-17 [doi]

Increasing the accuracy of SAT-based debuggingAndrÃ© SÃ¼lflow, GÃ¶rschwin Fey, CÃ©cile Braunstein, Ulrich KÃ¼hne, Rolf Drechsler. date 2009: 1326-1331 [doi]

Evaluation of Cardinality Constraints on SMT-Based DebuggingAndrÃ© SÃ¼lflow, Robert Wille, GÃ¶rschwin Fey, Rolf Drechsler. ismvl 2009: 298-303 [doi]

A fast untestability proof for SAT-based ATPGDaniel Tille, Rolf Drechsler. ddecs 2009: 38-43 [doi]

Equivalence Checking of Reversible CircuitsRobert Wille, Daniel GroÃŸe, D. Michael Miller, Rolf Drechsler. ismvl 2009: 324-330 [doi]

Reversible Logic Synthesis with Output PermutationRobert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler. vlsid 2009: 189-194 [doi]

Debugging of Toffoli networksRobert Wille, Daniel GroÃŸe, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler. date 2009: 1284-1289 [doi]

BDD-based synthesis of reversible logic for large functionsRobert Wille, Rolf Drechsler. dac 2009: 270-275 [doi]

SMT-based stimuli generation in the SystemC Verification libraryRobert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler. fdl 2009: 1-6 [doi]

2008

Logic Minimization and Testability of 2-SPP NetworksAnna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa. tcad, 27(7):1190-1202, 2008. [doi]

On Acceleration of SAT-Based ATPG for Industrial DesignsRolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille. tcad, 27(7):1329-1333, 2008. [doi]

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay FaultsStephan Eggersglüß, Rolf Drechsler. ismvl 2008: 94-99 [doi]

Automatic Fault Localization for Property CheckingGörschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler. tcad, 27(6):1138-1149, 2008. [doi]

A Basis for Formal Robustness CheckingGörschwin Fey, Rolf Drechsler. isqed 2008: 784-789 [doi]

On the construction of small fully testable circuits with low depthGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler. mam, 32(5-6):263-269, 2008. [doi]

Robustness and usability in modern design flowsGörschwin Fey, Rolf Drechsler. Springer, 2008.

Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. ProceedingsMario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang, editors, Volume 4974 of Lecture Notes in Computer Science, Springer, 2008.

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don t CaresDaniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. ismvl 2008: 214-219 [doi]

Analyzing Functional Coverage in Bounded Model CheckingDaniel Große, Ulrich Kühne, Rolf Drechsler. tcad, 27(7):1305-1314, 2008. [doi]

Contradiction Analysis for Constraint-based Random SimulationDaniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler. fdl 2008: 130-135 [doi]

Modeling and proving functional completeness in formal verification of counting headsSebastian Kinder, Rolf Drechsler. STTT, 10(6):521-534, 2008. [doi]

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking FlowUlrich Kühne, Daniel Große, Rolf Drechsler. mtv 2008: 88-93 [doi]

Comparative Study by Solving the Test Compaction ProblemDoina Logofatu, Rolf Drechsler. ismvl 2008: 44-49 [doi]

Adaptive Branch and Bound Using SAT to Estimate False CrosstalkMurthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler. isqed 2008: 508-513 [doi]

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrivalSujan Pandey, Rolf Drechsler. aspdac 2008: 601-606 [doi]

Process variations aware robust on-chip bus architecture synthesis for MPSoCsSujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner. iscas 2008: 2989-2992 [doi]

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCsSujan Pandey, Rolf Drechsler. date 2008: 206-211 [doi]

Automatic Generation of Complex Properties for Hardware DesignsFrank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke. date 2008: 545-548 [doi]

Improved SAT-based Reachability Analysis with Observability Don t CaresSean Safarpour, Andreas G. Veneris, Rolf Drechsler. jsat, 5(1-4):1-25, 2008. [doi]

Using unsatisfiable cores to debug multiple design errorsAndré Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler. glvlsi 2008: 77-82 [doi]

Incremental SAT Instance Generation for SAT-based ATPGDaniel Tille, Rolf Drechsler. ddecs 2008: 68-73 [doi]

RevLib: An Online Resource for Reversible Functions and Reversible CircuitsRobert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler. ismvl 2008: 220-225 [doi]

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean SatisfiabilityRobert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler. isvlsi 2008: 411-416 [doi]

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model CheckingRobert Wille, GÃ¶rschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler. dsd 2008: 542-549 [doi]

2007

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDLMahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler. ismvl 2007: 50 [doi]

Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?Rolf Drechsler, Andreas Breiter. ICSOFT 2007: 409-416

Experimental Studies on SAT-Based ATPG for Gate Delay FaultsStephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel. ismvl 2007: 6 [doi]

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay FaultsStephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel. memocode 2007: 181-187 [doi]

SAT-based ATPG for Path Delay Faults in Sequential CircuitsStephan Eggersglüß, Görschwin Fey, Rolf Drechsler. iscas 2007: 3671-3674 [doi]

On the Construction of Small Fully Testable Circuits with Low DepthGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler. dsdm 2007: 563-569 [doi]

Reusing Learned Information in SAT-based ATPGGörschwin Fey, Tim Warode, Rolf Drechsler. vlsid 2007: 69-76 [doi]

Visualization of SystemC DesignsChristian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard. iscas 2007: 413-416 [doi]

Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, ProceedingsMario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Muddassar Farooq, Andreas Fink, Evelyne Lutton, Penousal Machado, Stefan Minner, Michael O Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Hideyuki Takagi, Sima Uyar, Shengxiang Yang, editors, Volume 4448 of Lecture Notes in Computer Science, Springer, 2007.

PrefaceSabine Glesner, Jens Knoop, Rolf Drechsler. ENTCS, 190(4):1-2, 2007. [doi]

Measuring the Quality of a SystemC Testbench by using Code Coverage TechniquesDaniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler. fdl 2007: 146-151 [doi]

Exact sat-based toffoli network synthesisDaniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler. glvlsi 2007: 96-101 [doi]

Proving Completeness of Properties in Formal Verification of Counting Heads for RailwaysSebastian Kinder, Rolf Drechsler. dsdm 2007: 396-403 [doi]

Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems)Beate Muranko, Rolf Drechsler. it, 49(2):110, 2007. [doi]

Co-synthesis of custom on-chip bus and memory for MPSoC architecturesSujan Pandey, Christian Genz, Rolf Drechsler. vlsi 2007: 304-307 [doi]

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemCAndré Sülflow, Rolf Drechsler. ismvl 2007: 42 [doi]

Instance Generation for SAT-based ATPGDaniel Tille, Görschwin Fey, Rolf Drechsler. ddecs 2007: 153-156

SWORD: A SAT like prover using word level informationRobert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler. vlsi 2007: 88-93 [doi]

PreviousNext

All Publications

Publications by Year

Publications by Type

Publications by Tag

Publications by Venue

Publications by Author

Publications by Top Terms

Researchr

Publications by 'Rolf Drechsler'

2012

2011

2010

2009

2008

2007