Savithri Sundareswaran - researchr alias

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Viewing Publication 1 - 25 from 25

2019

SLECTS: Slew-Driven Clock Tree SynthesisWeicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang. tvlsi, 27(4):864-874, 2019. [doi]

2015

Decoupling Capacitance Design Strategies for Power Delivery Networks with Power GatingTong Xu, Peng Li, Savithri Sundareswaran. todaes, 20(3):38, 2015. [doi]

2011

A sensitivity-aware methodology to improve cell layouts for DFM guidelinesSavithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin. isqed 2011: 431-436 [doi]

2010

Total sensitivity based dfm optimization of standard library cellsYongchan Ban, Savithri Sundareswaran, David Z. Pan. ispd 2010: 113-120 [doi]

2009

Characterization of sequential cells for constraint sensitivitiesSavithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal. isqed 2009: 74-79 [doi]

2008

2007

2006

Optimal placement of power-supply pads and pinsMin Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. tcad, 25(1):144-154, 2006. [doi]

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programmingMin Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu. dac 2006: 217-222 [doi]

2004

A stochastic approach To power grid analysisSanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. dac 2004: 171-176 [doi]

Optimal placement of power supply pads and pinsMin Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda. dac 2004: 165-170 [doi]

2003

2002

Slope propagation in static timing analysisDavid T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran. tcad, 21(10):1180-1195, 2002. [doi]

2001

On the interaction of power distribution network with substrateRajendran Panda, Savithri Sundareswaran, David Blaauw. islped 2001: 388-393 [doi]

2000

Slope Propagation in Static Timing AnalysisDavid Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda. iccad 2000: 338-343

An Assertion Based Technique for Transistor Level Dynamic Power EstimationSavithri Sundareswaran, R. Venkatesan, S. Bhaskar. vlsid 2000: 34-37 [doi]

1999

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing AnalysisSavithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury. vlsid 1999: 175-180 [doi]

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