Sharad Malik - researchr alias

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2010

Utility of transaction-level hardware models in refinement checkingYogesh S. Mahajan, Sharad Malik. hldvt 2010: 121-128 [doi]

Runtime checking of serializability in software transactional memoryArnab Sinha, Sharad Malik. ipps 2010: 1-12 [doi]

2009

PrefaceAarti Gupta, Sharad Malik. fmsd, 35(1):1, 2009. [doi]

Boolean satisfiability from theoretical hardness to practical successSharad Malik, Lintao Zhang. CACM, 52(8):76-82, 2009. [doi]

Supporting RTL flow compatibility in a microarchitecture-level design frameworkDaniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik. codes 2009: 343-352 [doi]

Conflict-Driven Clause Learning SAT SolversJoÃ£o P. Marques Silva, InÃªs Lynce, Sharad Malik. In Armin Biere, Marijn Heule, Hans van Maaren, Toby Walsh, editors, Handbook of Satisfiability. Volume 185 of Frontiers in Artificial Intelligence and Applications, pages 131-153, IOS Press, 2009. [doi]

2008

Runtime Validation of Transactional Memory SystemsKaiyu Chen, Sharad Malik, Priyadarsan Patra. isqed 2008: 750-756 [doi]

Runtime validation of memory ordering using constraint graph checkingKaiyu Chen, Sharad Malik, Priyadarsan Patra. hpca 2008: 415-426 [doi]

Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, ProceedingsAarti Gupta, Sharad Malik, editors, Volume 5123 of Lecture Notes in Computer Science, Springer, 2008.

Hardware Verification: Techniques, Methodology and SolutionsSharad Malik. TACAS 2008: 1 [doi]

Declarative Infrastructure Configuration Synthesis and DebuggingSanjai Narain, Gary Levin, Sharad Malik, Vikram Kaul. jnsm, 16(3):235-258, 2008. [doi]

Challenges and Solutions for Late- and Post-Silicon DesignJan M. Rabaey, Sharad Malik. dt, 25(4):296-302, 2008. [doi]

Exploiting Circuit Reconvergence through Static Learning in CNF SAT SolversYinlei Yu, Cameron Brien, Sharad Malik. vlsid 2008: 461-468 [doi]

2007

2006

Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual AnalysisCameron Brien, Sharad Malik. FMCAD 2006: 49-50 [doi]

Dependable Multithreaded Processing Using Runtime ValidationKaiyu Chen, Sharad Malik. prdc 2006: 275-286 [doi]

On Solving the Partial MAX-SAT ProblemZhaohui Fu, Sharad Malik. sat 2006: 252-265 [doi]

Solving the minimum-cost satisfiability problem using SAT based branch-and-bound searchZhaohui Fu, Sharad Malik. iccad 2006: 852-859 [doi]

Solving Quantified Boolean Formulas with Circuit Observability Don t CaresDaijue Tang, Sharad Malik. sat 2006: 368-381 [doi]

The Liberty Simulation Environment: A deliberate approach to high-level system modelingManish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August. tocs, 24(3):211-249, 2006. [doi]

Lemma Learning in SMT on Linear ConstraintsYinlei Yu, Sharad Malik. sat 2006: 142-155 [doi]

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulationXinping Zhu, Wei Qin, Sharad Malik. tvlsi, 14(7):707-716, 2006. [doi]

2005

Achieving Structural and Composable Modeling of Complex SystemsDavid I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann. ijpp, 33(2-3):81-101, 2005. [doi]

Complementary use of runtime validation and model checkingAli Alphan Bayazit, Sharad Malik. iccad 2005: 1052-1059

Considering Circuit Observability Don t Cares in CNF SatisfiabilityZhaohui Fu, Yinlei Yu, Sharad Malik. date 2005: 1108-1113 [doi]

A Case for Runtime Validation of HardwareSharad Malik. hvc 2006: 30-42 [doi]

A Study of Architecture Description Languages from a Model-based PerspectiveWei Qin, Sharad Malik. mtv 2005: 3-11 [doi]

Symmetry Reduction in SAT-Based Model CheckingDaijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip. cav 2005: 125-138 [doi]

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip NetworksHangsheng Wang, Li-Shiuan Peh, Sharad Malik. date 2005: 1238-1243 [doi]

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximationFen Xie, Margaret Martonosi, Sharad Malik. islped 2005: 287-292 [doi]

Efficient behavior-driven runtime dynamic voltage scaling policiesFen Xie, Margaret Martonosi, Sharad Malik. codes 2005: 105-110 [doi]

Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practiceYinlei Yu, Sharad Malik. aspdac 2005: 1047-1051 [doi]

2004

Achieving Structural and Composable Modeling of Complex SystemsDavid I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai. ipps 2004: [doi]

The design of dynamically reconfigurable datapath coprocessorsZhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo. tecs, 3(2):361-384, 2004. [doi]

Zchaff2004: An Efficient SAT SolverYogesh S. Mahajan, Zhaohui Fu, Sharad Malik. sat 2005: 360-375 [doi]

Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004Sharad Malik, Limor Fix, Andrew B. Kahng, editors, ACM, 2004.

Guest Editors Introduction: Exploring Synergies for Design VerificationCarl Pixley, Sharad Malik. dt, 21(6):461-463, 2004. [doi]

A formal concurrency model based architecture description language for synthesis of software development toolsWei Qin, Subramanian Rajagopalan, Sharad Malik. lctrts 2004: 47-56 [doi]

A Comparative Study of 2QBF AlgorithmsDarsh P. Ranjan, Daijue Tang, Sharad Malik. sat 2004: [doi]

Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter ProblemsDaijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik. sat 2004: [doi]

Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter ProblemsDaijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik. sat 2005: 292-305 [doi]

Facilitating reuse in hardware models with enhanced type inferenceManish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August. codes 2004: 86-91 [doi]

Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modelingFen Xie, Margaret Martonosi, Sharad Malik. taco, 1(3):323-367, 2004. [doi]

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for MultiprocessingXinping Zhu, Sharad Malik. date 2004: 1244-1249 [doi]

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulationXinping Zhu, Wei Qin, Sharad Malik. codes 2004: 66-71 [doi]

2003

Automated synthesis of efficient binary decoders for retargetable software toolkitsWei Qin, Sharad Malik. dac 2003: 764-769 [doi]

Flexible and Formal Modeling of Microprocessors with Application to Retargetable SimulationWei Qin, Sharad Malik. date 2003: 10556-10561 [doi]

Modeling and Integration of Peripheral Devices in Embedded SystemsShaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi. date 2003: 10136-10141 [doi]

Synthesizing operating system based device drivers in embedded systemsShaojie Wang, Sharad Malik. codes 2003: 37-44 [doi]

Power-driven Design of Router Microarchitectures in On-chip NetworksHangsheng Wang, Li-Shiuan Peh, Sharad Malik. euromicro 2003: 105-116 [doi]

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand RoutersHangsheng Wang, Li-Shiuan Peh, Sharad Malik. micro, 23(1):26-35, 2003. [doi]

Compile-time dynamic voltage scaling settings: opportunities and limitsFen Xie, Margaret Martonosi, Sharad Malik. PLDI 2003: 49-62 [doi]

Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of AlgorithmsLintao Zhang, Sharad Malik. sat 2004: 287-298 [doi]

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other ApplicationsLintao Zhang, Sharad Malik. date 2003: 10880-10885 [doi]

2002

Datapath Merging and Interconnection Sharing for Reconfigurable ArchitecturesGuido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano. isss 2002: 38-43 [doi]

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solverMalay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik. dac 2002: 747-750 [doi]

Exploiting operation level parallelism through dynamically reconfigurable datapathsZhining Huang, Sharad Malik. dac 2002: 337-342 [doi]

From ASIC to ASIP: The Next Design DiscontinuityKurt Keutzer, Sharad Malik, A. Richard Newton. iccd 2002: 84-90 [doi]

Developing Architectural Platforms: A Disciplined ApproachAndrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik. dt, 19(6):6-16, 2002. [doi]

Limits of Using Signatures for Permutation Independent Boolean ComparisonJanett Mohnke, Paul Molitor, Sharad Malik. fmsd, 21(2):167-191, 2002.

Architecture Description Languages for Retargetable CompilationWei Qin, Sharad Malik. In The Compiler Design Handbook. pages 535-564, 2002.

Design Tools for Application Specific Embedded ProcessorsWei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh. emsoft 2002: 319-333 [doi]

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal ProcessorsSubramanian Rajagopalan, Sharad Malik. In The Compiler Design Handbook. pages 603-630, 2002.

Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey. dac 2002: 479 [doi]

Orion: a power-performance simulator for interconnection networksHangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik. euromicro 2002: 294-305 [doi]

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand RoutersHangsheng Wang, Li-Shiuan Peh, Sharad Malik. hoti 2002: 21-27 [doi]

Conflict driven learning in a quantified Boolean Satisfiability solverLintao Zhang, Sharad Malik. iccad 2002: 442-449 [doi]

The Quest for Efficient Boolean Satisfiability SolversLintao Zhang, Sharad Malik. cade 2002: 295-313 [doi]

The Quest for Efficient Boolean Satisfiability SolversLintao Zhang, Sharad Malik. cav 2002: 17-36 [doi]

Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula EvaluationLintao Zhang, Sharad Malik. cp 2002: 200-215 [doi]

A hierarchical modeling framework for on-chip communication architecturesXinping Zhu, Sharad Malik. iccad 2002: 663-671 [doi]

2001

Using complete-1-distinguishability for FSM equivalence checkingPranav Ashar, Aarti Gupta, Sharad Malik. todaes, 6(4):569-590, 2001. [doi]

Retargetable static timing analysis for embedded softwareKaiyu Chen, Sharad Malik, David I. August. isss 2001: 39-44

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDsAarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik. iccad 2001: 286-292 [doi]

Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networksZhining Huang, Sharad Malik. date 2001: 735 [doi]

Embedded Software Implementation Tools for Fully Programmable Application Specific SystemsSharad Malik. emsoft 2001: 254-256 [doi]

Application of BDDs in Boolean matching techniques for formal logic combinational verificationJanett Mohnke, Paul Molitor, Sharad Malik. STTT, 3(2):207-216, 2001. [doi]

Chaff: Engineering an Efficient SAT SolverMatthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik. dac 2001: 530-535 [doi]

Optimal Live Range Merge for Address Register Allocation in Embedded ProgramsGuilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik. CC 2001: 274-288 [doi]

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelismSubramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama. tcad, 20(11):1319-1328, 2001. [doi]

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based DesignMarco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli. dac 2001: 667-672 [doi]

Efficient Conflict Driven Learning in Boolean Satisfiability SolverLintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik. iccad 2001: 279-285 [doi]

Accelerating boolean satisfiability through application specific processingYing Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan. isss 2001: 244-249

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability ProblemYing Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan. iccd 2001: 447-452

2000

Incremental CADOlivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh. iccad 2000: 236-243

Automated cache optimizations using CME driven diagnosisSomnath Ghosh, Margaret Martonosi, Sharad Malik. ics 2000: 316-326 [doi]

Processor Evaluation in an Embedded Systems Design EnvironmentT. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik. vlsid 2000: 98-103 [doi]

Embedded systems education (panel abstract)Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf. dac 2000: 519 [doi]

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraintsSubramanian Rajagopalan, Manish Vachharajani, Sharad Malik. cases 2000: 157-164 [doi]

Simultaneous reference allocation in code generation for dual data memory bank ASIPsAshok Sudarsanam, Sharad Malik. todaes, 5(2):242-264, 2000. [doi]

Exact memory size estimation for array computationsYing Zhao, Sharad Malik. tvlsi, 8(5):517-521, 2000. [doi]

1999

Cache miss equations: a compiler framework for analyzing and tuning memory behaviorSomnath Ghosh, Margaret Martonosi, Sharad Malik. TOPLAS, 21(4):703-746, 1999. [doi]

Performance estimation of embedded software with instruction cache modelingYau-Tsun Steven Li, Sharad Malik, Andrew Wolfe. todaes, 4(3):257-279, 1999. [doi]

Establishing latch correspondence for sequential circuits using distinguishing signaturesJanett Mohnke, Paul Molitor, Sharad Malik. integration, 27(1):33-46, 1999. [doi]

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processorSreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik. codes 1999: 2-6 [doi]

Exact Memory Size Estimation for Array Computations without Loop UnrollingYing Zhao, Sharad Malik. dac 1999: 811-816 [doi]

Using configurable computing to accelerate Boolean satisfiabilityPeixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. tcad, 18(6):861-868, 1999. [doi]

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