Shih-Lien Lu - researchr alias

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2011

2010

Resilient microprocessor design for high performance & energy efficiencyKeith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De. islped 2010: 355-356 [doi]

Automatic multithreaded pipeline synthesis from transactional datapath specificationsEriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam. dac 2010: 314-319 [doi]

Automatic pipelining from transactional datapath specificationsEriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu. date 2010: 1001-1004 [doi]

Resilient design in scaled CMOS for energy efficiencyJames Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De. aspdac 2010: 625 [doi]

Reducing cache power with low-cost, multi-bit error-correcting codesChris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu. isca 2010: 83-93 [doi]

2009

Circuit techniques for dynamic variation toleranceKeith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar. dac 2009: 4-7 [doi]

Improving cache lifetime reliability at ultra-low voltagesZeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu. micro 2009: 89-99 [doi]

Low power adaptive pipeline based on instruction isolationSeung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh. isqed 2009: 788-793 [doi]

Resilient circuits - Enabling energy-efficient performance and reliabilityJames Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik. iccad 2009: 71-73 [doi]

Trading Off Cache Capacity for Low-Voltage OperationChris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu. micro, 29(1):96-103, 2009. [doi]

2008

2007

2006

Design, implementation, and verification of active cache emulator (ACE)Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu. fpga 2006: 63-72 [doi]

2005

Improving branch prediction accuracy with parallel conservative correctorsChunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Chen. cf 2005: 334-341 [doi]

Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-CEriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu. ics 2005: 12-20 [doi]

2004

Efficient Victim Mechanism on Sector Cache OrganizationChunrong Lai, Shih-Lien Lu. APCSAC 2004: 16-29 [doi]

Speeding Up Processing with Approximation CircuitsShih-Lien Lu. Computer, 37(3):67-73, 2004. [doi]

2003

Hardware-based Pointer Data PrefetcherShih-Chang Lai, Shih-Lien Lu. iccd 2003: 290-298 [doi]

Implementation of HW im - A Real-Time Configurable Cache SimulatorShih-Lien Lu, Konrad Lai. fpl 2003: 638-647 [doi]

2002

2000

Performance improvement with circuit-level speculationTong Liu, Shih-Lien Lu. euromicro 2000: 348-355 [doi]

1998

Non-Stalling CounterFlow ArchitectureMichael F. Miller, Kenneth J. Janik, Shih-Lien Lu. hpca 1998: 334-341 [doi]

1997

Advances of the Counterflow Pipeline MicroarchitectureKenneth J. Janik, Shih-Lien Lu, Michael F. Miller. hpca 1997: 230-236 [doi]

1996

Efficient arithmetic using self-timingRavichandran Ramachandran, Shih-Lien Lu. tvlsi, 4(4):445-454, 1996. [doi]

1995

Design of a static MIMD data flow processor using micropipelinesChih-Ming Chang, Shih-Lien Lu. tvlsi, 3(3):370-378, 1995. [doi]

Implementation of micropipelines in enable/disable CMOS differential logicShih-Lien Lu. tvlsi, 3(2):338-341, 1995. [doi]

1988

Device and circuit simulation interface for an integrated VLSI design environmentChung-Ping Wan, Bing J. Sheu, Shih-Lien Lu. tcad, 7(9):998-1004, 1988. [doi]