Shinji Tomita - researchr alias

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2011

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline DepthJun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita. jcst, 26(2):292-301, 2011. [doi]

2008

2007

Optimal pipeline depth with pipeline stage unification adoptionJun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita. sigarch, 35(5):3-9, 2007. [doi]

2005

Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification AdoptionJun Yao, Hajime Shimada, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita. ishpc 2008: 494-507 [doi]

2004

2003

A Web-Based Education Tool for Collaborative Learning of Assembly ProgrammingYoshiro Imai, Shinji Tomita. iadis 2003: 703-710

Bilateral Tradings with and without Strategic ThinkingShinji Tomita, Akira Namatame. mabs 2003: 73-88 [doi]

2002

Development of an Education Tool for Computer SystemYoshiro Imai, Shinji Tomita, Haruo Niimi, Hitoshi Inomo, Wataru Shiraki, Hiroshi Ishikawa. ICCE 2002: 1309-1310

2001

A high-speed dynamic instruction scheduling scheme for superscalar processorsMasahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori. euromicro 2001: 225-236 [doi]

1999

A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPARAtsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. ijpp, 27(2):97-109, 1999.

High Performance Computing, Second International Symposium, ISHPC 99, Kyoto, Japan, May 26-28, 1999, ProceedingsConstantine D. Polychronopoulos, Kazuki Joe, Akira Fukuda, Shinji Tomita, editors, Volume 1615 of Lecture Notes in Computer Science, Springer, 1999.

1998

Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPARShin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. IEEEpact 1998: 426-433 [doi]

1997

1996

Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel ComputerHesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. ics 1996: 197-204 [doi]

1995

Amon: A Parallel Slice Algorithm for Wire RoutingHesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. ics 1995: 200-208 [doi]

1993

A distributed shared memory multiprocessor ASURA: memory and cache architectureShin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita. sc 1993: 740-749 [doi]

1992

Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architectureTetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita. ics 1992: 272-281 [doi]

1989

1986

ISDN and X25 - ResponseShinji Tomita. ifip 1986: 185-188

A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp MachinesShinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara. isca 1986: 280-289

1983

A User-Microprogrammable, Local Host Computer With Low-Level ParallelismShinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara. isca 1983: 151-157

1980

A Dynamically Microprogammable Computer with Low-Level ParallelismHiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama. TC, 29(7):577-595, 1980.

Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level ParallelismKiyoshi Shibayama, Shinji Tomita, Hiroshi Hagiwara, Katsuhiro Yamazaki, Toshiaki Kitamura. ifip 1980: 181-186

1977

Hardware Organization of a Low Level Parallel ProcessorShinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara. ifip11-9 1977: 855-860

1971

On-Line, Real-Time, Multiple-Speech Output SystemToshiyuki Sakai, Kenji Ohtani, Shinji Tomita. ifip 1971: 686-690