Tad A. Kwasniewski - researchr alias

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Viewing Publication 1 - 39 from 39

2017

On-die power grid broadband model determination using a priori narrowband measurementsLeonard MacEachem, Xin-jie Wang, Tad A. Kwasniewski. mwscas 2017: 1493-1496 [doi]

2012

A DLL-based fractional-N frequency synthesizer with a programmable injection clockHaizheng Guo, Tad A. Kwasniewski. ccece 2012: 1-4 [doi]

2011

A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications systemHarry Tai, Peter Noel, Tad A. Kwasniewski. socc 2011: 114-117 [doi]

2010

Optimized LNA for analog RF front-end circuit in brain-machine interfaceHaizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot. wcnis 2010: 147-150 [doi]

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression EliminationH. Ho, V. Szwarc, Tad A. Kwasniewski. vlsisp, 61(3):353-365, 2010. [doi]

2009

2008

Low complexity sphere decoding algorithmsRamin Shariat-Yazdi, Tad A. Kwasniewski. iswcs 2008: 438-442 [doi]

2007

A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS TechnologyMuhammad Usama, Tad A. Kwasniewski. iscas 2007: 3047-3050 [doi]

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOSJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. cicc 2007: 543-546 [doi]

2006

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitationsWm. Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel. dac 2006: 1013-1016 [doi]

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency DividerQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. ccece 2006: 701-704 [doi]

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication SystemQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. socc 2006: 123-126 [doi]

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur ReductionQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. tcas, 53-II(11):1205-1209, 2006. [doi]

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced SpurQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. cicc 2006: 761-764 [doi]

A 0.18µm CMOS clock and data recovery circuit with extended operation rangeMiao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang. iscas 2006: [doi]

A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane ApplicationsMiao Li, Tad A. Kwasniewski, Shoujun Wang. apccas 2006: 1039-1042 [doi]

An eye detection technique for clock and data recovery applicationsJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. iscas 2006: [doi]

2005

An all-digital data recovery circuit optimization using Matlab/SimulinkS. I. Ahmed, Tad A. Kwasniewski. iscas 2005: 4485-4488 [doi]

A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial BackplaneCharles E. Berndt, Tad A. Kwasniewski. iwsoc 2005: 149-153 [doi]

Decision feedback equalization for high-speed backplane data communicationsJing Chen, Miao Li, Tad A. Kwasniewski. iscas 2005: 1274-1277 [doi]

Turbo Codes - Digital IC DesignMoeed Israr, Tad A. Kwasniewski. iwsoc 2005: 341-346 [doi]

Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data CommunicationsMiao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang. iwsoc 2005: 500-502 [doi]

A 0.18µm CMOS transceiver design for high-speed backplane data communicationsMiao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang. iscas 2005: 1158-1161 [doi]

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technologyMiao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao. aspdac 2005: 679-682 [doi]

A signal integrity-based link performance simulation platformYuming Tao, William Bereza, Rakesh H. Patel, Sergey Shumarayev, Tad A. Kwasniewski. cicc 2005: 725-728 [doi]

PLL-Based Fractional-N Frequency SynthesizersFarhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski. iwsoc 2005: 85-91 [doi]

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCOJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. iastedCCS 2005: 128-131

2004

2.4 GHz RF down-conversion mixers in standard CMOS technologyArif A. Siddiqi, Tad A. Kwasniewski. iscas 2004: 321-324 [doi]

Design and comparison of CMOS Current Mode Logic latchesMuhammad Usama, Tad A. Kwasniewski. iscas 2004: 353-356

2003

A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizerJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. cicc 2003: 301-304 [doi]

1999

1996

Is High Frequency Analog DFT Possible?Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik. vts 1996: 214-215 [doi]

1994

A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systemsD. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc. vtc 1994: 520-524 [doi]

A chip set for pipeline and parallel pipeline FFT architecturesV. Szwarc, L. Desormeaux, W. Wong, C. P. S. Yeung, C. H. Chan, Tad A. Kwasniewski. vlsisp, 8(3):253-265, 1994. [doi]

1991

Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber LoopsP. Mohanraj, David D. Falconer, Tad A. Kwasniewski. jsac, 9(6):871-875, 1991.

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Publications by 'Tad A. Kwasniewski'

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2017

2012

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2009

2008

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2006

2005

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1999

1996

1994

1991

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