Terumine Hayashi - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 26 from 26

2009

Obstacle to training SpikeProp networks - Cause of surges in training process -Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi. ijcnn 2009: 3062-3066 [doi]

2008

Shape of error surfaces in SpikePropMasaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi. ijcnn 2008: 840-844 [doi]

2007

Descriptive Answer Clustering System for Immediate FeedbackKazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita. ICCE 2007: 37-40

Enhancing both generalization and fault tolerance of multilayer neural networksHaruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi. ijcnn 2007: 1429-1433 [doi]

2006

Low Power Oriented Test Modification and Compression Techniques for Scan Based Core TestingTerumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita. ats 2006: 327-332 [doi]

2005

On Test Data Compression Using Selective Don t-Care IdentificationTerumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase. jcst, 20(2):210-215, 2005. [doi]

A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test ArchitectureTsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa. ats 2005: 366-371 [doi]

2004

Test data compression technique using selective don t-care identificationTerumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase. aspdac 2004: 230-233 [doi]

2003

Manipulation of hidden units activities for fault tolerant multi-layer neural networksYusei Katsuda, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi. cira 2003: 19-24 [doi]

Between-Core Vector Overlapping for Test Cost Reduction in Core TestingTsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka. ats 2003: 268-273 [doi]

2001

An enhanced fault model for high defect coverageJunzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi. scjapan, 32(6):36-44, 2001. [doi]

Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG SystemsTsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi. ats 2001: 76-81 [doi]

2000

Cyclic greedy generation method for limited number of IDDQ testsTsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi. ats 2000: 362 [doi]

Evaluation Function for Fault Tolerant Multi-Layer Neural NetworksHaruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita. ijcnn 2000: 521-526 [doi]

1999

A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational CircuitsTsuyoshi Shinogi, Terumine Hayashi. ats 1999: 164 [doi]

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuitsTsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki. scjapan, 30(7):55-68, 1999. [doi]

A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit PartitionKai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi. aspdac 1999: 291-294 [doi]

1998

On a Logical Fault Model H1SGLF for Enhancing Defect CoverageJunzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi. ats 1998: 102-107 [doi]

A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging FaultTsuyoshi Shinogi, Terumine Hayashi. vts 1998: 112-117 [doi]

1997

Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPLTsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki. ats 1997: 16-21 [doi]

An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuitsKai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita. aspdac 1997: 107-112 [doi]

1993

Sequential circuit test generation by real number simulationKazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi. scjapan, 24(9):64-75, 1993. [doi]

1992

Sequential Test Generation Based on Real-Value LogicKazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi. itc 1992: 41-48

1991

Timing-Oriented Routers for PCB Layout Design of High-Performance ComputersYutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani. iccad 1991: 332-335

1989

Enhanced Delay Test Generator for High-Speed Logic LSIsKazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama. itc 1989: 161-165

1986

A delay test system for high speed logic LSI sKuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi. dac 1986: 786-790 [doi]

Sign in or sign up to see more results.

runs on WebDSL